forked from M-Labs/artiq-zynq
frameline GW: rename downconn to channels
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8e8d873960
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61183d1c6d
@ -57,10 +57,10 @@ class End_Of_Line_Inserter(Module):
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]
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class Stream_Arbiter(Module):
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def __init__(self, n_downconn):
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self.n_ext_active = Signal(max=n_downconn)
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def __init__(self, n_channels):
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self.n_ext_active = Signal(max=n_channels)
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self.sinks = [stream.Endpoint(word_layout_dchar) for _ in range(n_downconn)]
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self.sinks = [stream.Endpoint(word_layout_dchar) for _ in range(n_channels)]
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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@ -633,8 +633,8 @@ class ROI(Module):
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])
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# # #
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#
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# TODO: remove the self. from self.roi_4x
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self.roi_4x = []
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for _ in range(4):
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self.roi_4x.append(Record([
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