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upconn GW: remove debug buf

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This commit is contained in:
morgan 2025-01-14 12:41:29 +08:00
parent 02913d2fda
commit 5ef521f0f6
1 changed files with 1 additions and 48 deletions
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49
src/gateware/cxp_upconn.py
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@ -85,38 +85,6 @@ class SERDES_10bits(Module):
)
]
class Debug_buffer(Module,AutoCSR):
def __init__(self, layout):
self.sink_stb = Signal()
self.sink_ack = Signal()
self.sink_data = Signal(8)
self.sink_k = Signal()
# # #
self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 512)
self.sync += [
buf_out.sink.stb.eq(self.sink_stb),
self.sink_ack.eq(buf_out.sink.ack),
buf_out.sink.data.eq(self.sink_data),
buf_out.sink.k.eq(self.sink_k),
]
self.inc = CSR()
self.dout_pak = CSRStatus(8)
self.kout_pak = CSRStatus()
self.dout_valid = CSRStatus()
self.sync += [
# output
buf_out.source.ack.eq(self.inc.re),
self.dout_pak.status.eq(buf_out.source.data),
self.kout_pak.status.eq(buf_out.source.k),
self.dout_valid.status.eq(buf_out.source.stb),
]
class Transmitter(Module, AutoCSR):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads):
self.bitrate2x_enable = Signal()
@ -129,35 +97,20 @@ class Transmitter(Module, AutoCSR):
self.submodules.cg = cg = ClockGen(sys_clk_freq)
self.submodules.encoder = encoder = SingleEncoder(True)
self.submodules.debug_buf = debug_buf = Debug_buffer(char_layout)
oe = Signal()
self.sync += [
If(self.enable,
self.sink.ack.eq(0),
# DEBUG:
debug_buf.sink_stb.eq(0),
If(cg.clk,
oe.eq(1),
encoder.disp_in.eq(encoder.disp_out),
self.sink.ack.eq(1),
encoder.d.eq(self.sink.data),
encoder.k.eq(self.sink.k),
# DEBUG:
If(debug_buf.sink_ack,
debug_buf.sink_stb.eq(1),
debug_buf.sink_data.eq(self.sink.data),
debug_buf.sink_k.eq(self.sink.k),
)
)
).Else(
# DEBUG:
debug_buf.sink_stb.eq(0),
# no backpressure
# discard packets until tx is enabled
self.sink.ack.eq(1),
oe.eq(0),
)