diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index 3b44ee0..04caff5 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -8,6 +8,7 @@ from cxp_pipeline import *
 
 class CXP(Module, AutoCSR):
     def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.submodules.trig = TX_Trigger(cxp_phy_layout())
 
         self.submodules.upconn = UpConn_Interface(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
 
@@ -138,30 +139,63 @@ class UpConn_Interface(Module, AutoCSR):
             upconn_phy.tx_fifos.sink[2].k.eq(self.symbol2.r[8]),
         ]
 
+def K(x, y):
+    return ((y << 5) | x)
+
+# TODO: move this to cxp_pipeline, since it used K(x, y) :<
 class TX_Trigger(Module, AutoCSR):
-    def __init__(self):
+    def __init__(self, layout):
         # This module is mostly control by gateware
 
         self.trig_stb = Signal()
-        self.delay = Signal(max=240)
-
-        self.ack = Signal()
+        self.delay = Signal(8) # FIXME: use source instead 
+        self.linktrig_mode = Signal(max=4)
 
         # # #
 
-        self.submodules.trig_ack = trig_ack = Trigger_ACK(cxp_phy_layout())
-        self.submodules.buf_out = buf_out = stream.SyncFIFO(cxp_phy_layout(), 64)
 
-        tx_pipeline = [ trig_ack, buf_out]
+        self.submodules.code_src = code_src = Code_Source(layout, counts=3)
+        self.comb += [
+            code_src.stb.eq(self.trig_stb),
+            code_src.data.eq(self.delay),
+            code_src.k.eq(0)
+        ]
+
+        self.submodules.inserter_once = inserter_once = Code_Inserter(layout, counts=1, insert_infront=False)
+        self.submodules.inserter_twice = inserter_twice = Code_Inserter(layout, counts=2)
+
+        self.comb += [
+            inserter_once.k.eq(1),
+            inserter_twice.k.eq(1),
+            If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
+                inserter_once.data.eq(K(28, 2)),
+                inserter_twice.data.eq(K(28, 4)),
+            ).Else(
+                inserter_once.data.eq(K(28, 4)),
+                inserter_twice.data.eq(K(28, 2)),
+            )
+        ]
+        
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 64)
+
+        tx_pipeline = [ code_src, inserter_twice, inserter_once, buf_out]
+        # tx_pipeline = [ code_src, inserter_twice, buf_out]
 
         for s, d in zip(tx_pipeline, tx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
 
+        self.source = tx_pipeline[-1].source
+
 
         # DEBUG: INPUT
-        self.ack = CSR()
+        self.stb = CSR()
+        self.trig_delay = CSRStorage(8) 
+        self.linktrigger = CSRStorage(2)
+
         self.sync += [
-            trig_ack.ack.eq(self.ack.re),
+            self.trig_stb.eq(self.stb.re),
+            self.delay.eq(self.trig_delay.storage),
+            self.linktrig_mode.eq(self.linktrigger.storage),
         ]
 
         # DEBUG: OUTPUT