From 5e2b3360b919a6d673545d4f7c9809b770a1eff2 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Fri, 24 Jan 2025 13:11:34 +0800
Subject: [PATCH] phy fw: update csr

---
 src/libboard_artiq/src/cxp_phys.rs | 62 +++++++++++-------------------
 1 file changed, 22 insertions(+), 40 deletions(-)

diff --git a/src/libboard_artiq/src/cxp_phys.rs b/src/libboard_artiq/src/cxp_phys.rs
index 893eec2..9d3941d 100644
--- a/src/libboard_artiq/src/cxp_phys.rs
+++ b/src/libboard_artiq/src/cxp_phys.rs
@@ -1,10 +1,6 @@
-use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
-use libboard_zynq::timer::GlobalTimer;
 use log::info;
 
-use crate::pl::{csr, csr::CXP};
-
-pub const CXP_CHANNELS: u8 = csr::CXP_LEN as u8;
+use crate::pl::csr;
 
 #[derive(Clone, Copy, Debug)]
 #[allow(non_camel_case_types)]
@@ -18,8 +14,8 @@ pub enum CXP_SPEED {
     CXP_12,
 }
 
-pub fn setup(timer: &mut GlobalTimer) {
-    rx::setup(timer);
+pub fn setup() {
+    rx::setup();
     tx::setup();
     change_linerate(CXP_SPEED::CXP_1);
 }
@@ -57,21 +53,13 @@ mod tx {
 mod rx {
     use super::*;
 
-    pub fn setup(timer: &mut GlobalTimer) {
+    pub fn setup() {
         unsafe {
             csr::cxp_phys::rx_qpll_reset_write(1);
             info!("waiting for QPLL/CPLL to lock...");
             while csr::cxp_phys::rx_qpll_locked_read() != 1 {}
             info!("QPLL locked");
-
             csr::cxp_phys::rx_gtx_start_init_write(1);
-
-            // DEBUG: printout
-            info!("waiting for rx setup...");
-            timer.delay_us(50_000);
-            for ch in 0..CXP_CHANNELS {
-                info!("rx_phaligndone = {}", (CXP[ch as usize].rx_rxinit_phaligndone_read)());
-            }
         }
     }
 
@@ -113,11 +101,9 @@ mod rx {
 
         // DEBUG:
         // println!("RX GTX DRP:");
-        for ch in 0..CXP_CHANNELS {
-            // println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
-            gtx_write(ch, 0x88, div_reg);
-            // println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
-        }
+        // println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
+        gtx_write(0x88, div_reg);
+        // println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
     }
 
     fn change_cdr_cfg(speed: CXP_SPEED) {
@@ -164,33 +150,29 @@ mod rx {
             },
         };
 
-        for channel in 0..CXP_CHANNELS {
-            gtx_write(channel, 0x0A8, cdr_cfg.cfg_reg0);
-            gtx_write(channel, 0x0A9, cdr_cfg.cfg_reg1);
-            gtx_write(channel, 0x0AA, cdr_cfg.cfg_reg2);
-            gtx_write(channel, 0x0AB, cdr_cfg.cfg_reg3);
-            gtx_write(channel, 0x0AC, cdr_cfg.cfg_reg4);
-        }
+        gtx_write(0x0A8, cdr_cfg.cfg_reg0);
+        gtx_write(0x0A9, cdr_cfg.cfg_reg1);
+        gtx_write(0x0AA, cdr_cfg.cfg_reg2);
+        gtx_write(0x0AB, cdr_cfg.cfg_reg3);
+        gtx_write(0x0AC, cdr_cfg.cfg_reg4);
     }
 
     #[allow(dead_code)]
-    fn gtx_read(channel: u8, address: u16) -> u16 {
-        let channel = channel as usize;
+    fn gtx_read(address: u16) -> u16 {
         unsafe {
-            (CXP[channel].rx_gtx_daddr_write)(address);
-            (CXP[channel].rx_gtx_dread_write)(1);
-            while (CXP[channel].rx_gtx_dready_read)() != 1 {}
-            (CXP[channel].rx_gtx_dout_read)()
+            csr::cxp_phys::rx_gtx_daddr_write(address);
+            csr::cxp_phys::rx_gtx_dread_write(1);
+            while csr::cxp_phys::rx_gtx_dready_read() != 1 {}
+            csr::cxp_phys::rx_gtx_dout_read()
         }
     }
 
-    fn gtx_write(channel: u8, address: u16, value: u16) {
-        let channel = channel as usize;
+    fn gtx_write(address: u16, value: u16) {
         unsafe {
-            (CXP[channel].rx_gtx_daddr_write)(address);
-            (CXP[channel].rx_gtx_din_write)(value);
-            (CXP[channel].rx_gtx_din_stb_write)(1);
-            while (CXP[channel].rx_gtx_dready_read)() != 1 {}
+            csr::cxp_phys::rx_gtx_daddr_write(address);
+            csr::cxp_phys::rx_gtx_din_write(value);
+            csr::cxp_phys::rx_gtx_din_stb_write(1);
+            while csr::cxp_phys::rx_gtx_dready_read() != 1 {}
         }
     }