diff --git a/src/libboard_artiq/src/cxp_downconn.rs b/src/libboard_artiq/src/cxp_downconn.rs
index a6312e4..64b842e 100644
--- a/src/libboard_artiq/src/cxp_downconn.rs
+++ b/src/libboard_artiq/src/cxp_downconn.rs
@@ -65,39 +65,31 @@ fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
         csr::cxp::downconn_txenable_write(1);
 
         info!("waiting for rx to align...");
-        timer.delay_us(50_000);
+        // timer.delay_us(50_000);
         // while csr::cxp::downconn_rx_ready_read() != 1 {}
-        // info!("rx ready!");
+        info!("rx ready!");
 
-        // csr::cxp::data_3_write(data);
-        // csr::cxp::control_bit_3_write(control_bit);
-        // println!(
-        //     "data[0] = {:#04x} control bit = {:#b} encoded = {:#012b}",
-        //     csr::cxp::downconn_data_0_read(),
-        //     csr::cxp::downconn_control_bit_0_read(),
-        //     csr::cxp::downconn_encoded_0_read(),
-        // );
-        // println!(
-        //     "data[1] = {:#04x} control bit = {:#b} encoded = {:#012b}",
-        //     csr::cxp::downconn_data_1_read(),
-        //     csr::cxp::downconn_control_bit_1_read(),
-        //     csr::cxp::downconn_encoded_1_read(),
-        // );
+        println!("0xA8 = {:#06x}", read(0x62));
+        write(0x62, 0x001A);
+        println!("0xA8 = {:#06x}", read(0x62));
 
+        println!("shifted = {}", csr::cxp::downconn_shifted_read());
         // for _ in 0..20 {
         loop {
+            let data0 = csr::cxp::downconn_rxdata_0_read();
+            // let data1 = csr::cxp::downconn_rxdata_1_read();
+            let rxready = csr::cxp::downconn_rx_ready_read();
             // timer.delay_us(100);
-            println!(
-                "data = {:#022b} | rx ready = {}",
-                (csr::cxp::downconn_rxdata_0_read() as u32 | ((csr::cxp::downconn_rxdata_1_read() as u32) << 10)),
-                csr::cxp::downconn_rx_ready_read()
-            );
-            timer.delay_us(1_000_000);
-            // println!(
-            //     "data[0] = {:#012b} data[1] = {:#012b}",
-            //     csr::cxp::rxdata_0_read(),
-            //     csr::cxp::rxdata_1_read(),
-            // );
+            // timer.delay_us(1_000_000);
+            if data0 == 0b0101111100 || data0 == 0b1010000011 {
+                println!(
+                    "data[0] = {:#012b} comma = {} | rx ready = {}",
+                    data0,
+                    data0 == 0b0101111100 || data0 == 0b1010000011,
+                    rxready,
+                );
+                timer.delay_us(1_000_000);
+            }
             // println!(
             //     "decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
             //     csr::cxp::downconn_decoded_data_0_read(),
@@ -175,6 +167,26 @@ fn change_qpll_settings(speed: CXP_SPEED) {
     }
 }
 
+fn read(address: u16) -> u16 {
+    // DEBUG: DRPCLK need to be on for a few cycle before accessing other DRP ports
+    unsafe {
+        csr::cxp::downconn_gtx_daddr_write(address);
+        csr::cxp::downconn_gtx_dread_write(1);
+        while (csr::cxp::downconn_gtx_dready_read() != 1) {}
+        csr::cxp::downconn_gtx_dout_read()
+    }
+}
+
+fn write(address: u16, value: u16) {
+    // DEBUG: DRPCLK need to be on for a few cycle before accessing other DRP ports
+    unsafe {
+        csr::cxp::downconn_gtx_daddr_write(address);
+        csr::cxp::downconn_gtx_din_write(value);
+        csr::cxp::downconn_gtx_din_stb_write(1);
+        while (csr::cxp::downconn_gtx_dready_read() != 1) {}
+    }
+}
+
 pub mod txusrclk {
     use super::*;