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Unify Si5324 setup code with main ARTIQ repository [nfc]

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I chose the version from the main repository for two
reasons:
 - Explicitly specifying si5324_ref_input every time would
   not work for the different Kasli/… hardware versions.
 - Having `crystal_ref` as a setting in the configuration
   is misleading if it does not actually activate the crystal
   for use as a reference (but rather does
   `route_crystal_to_ckin2`).

Related m-labs/artiq commits:
 - 740543d4e284245248e3ff838c46505938dcae7a
 - 3c7a394eff553ab75a7ea78bdd17830366504dc6
This commit is contained in:
David Nadlinger 2022-12-12 23:17:49 +00:00
parent c281505aa0
commit 5c054cc901
2 changed files with 85 additions and 100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/libboard_artiq/src/si5324.rs
View File

@ -219,8 +219,11 @@ pub fn bypass(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()
Ok(()) Ok(())
} }
pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: &mut GlobalTimer) -> Result<()> { pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, ext_input: Input, timer: &mut GlobalTimer) -> Result<()> {
let s = map_frequency_settings(settings)?; let s = map_frequency_settings(settings)?;
// FREE_RUN=1 routes XA/XB to CKIN2.
let input = if settings.crystal_ref { Input::Ckin2 } else { ext_input };
let cksel_reg = match input { let cksel_reg = match input {
Input::Ckin1 => 0b00, Input::Ckin1 => 0b00,
Input::Ckin2 => 0b01, Input::Ckin2 => 0b01,

180
src/runtime/src/rtio_clocking.rs
View File

@ -115,123 +115,106 @@ fn init_drtio(timer: &mut GlobalTimer)
} }
} }
// Si5324 input to select for locking to an external clock.
#[cfg(has_si5324)]
const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin1;
#[cfg(has_si5324)] #[cfg(has_si5324)]
fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) { fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
let (si5324_settings, si5324_ref_input) = match clk { let si5324_settings = match clk {
RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
( si5324::FrequencySettings {
si5324::FrequencySettings { n1_hs : 10,
n1_hs : 10, nc1_ls : 4,
nc1_ls : 4, n2_hs : 10,
n2_hs : 10, n2_ls : 300,
n2_ls : 300, n31 : 6,
n31 : 6, n32 : 6,
n32 : 6, bwsel : 4,
bwsel : 4, crystal_ref: false
crystal_ref: false }
},
si5324::Input::Ckin1
)
}, },
RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
info!("using 100MHz reference to make 125MHz RTIO clock with PLL"); info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
( si5324::FrequencySettings {
si5324::FrequencySettings { n1_hs : 10,
n1_hs : 10, nc1_ls : 4,
nc1_ls : 4, n2_hs : 10,
n2_hs : 10, n2_ls : 260,
n2_ls : 260, n31 : 52,
n31 : 52, n32 : 52,
n32 : 52, bwsel : 4,
bwsel : 4, crystal_ref: false
crystal_ref: false }
},
si5324::Input::Ckin1
)
}, },
RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
info!("using 125MHz reference to make 125MHz RTIO clock with PLL"); info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
( si5324::FrequencySettings {
si5324::FrequencySettings { n1_hs : 5,
n1_hs : 5, nc1_ls : 8,
nc1_ls : 8, n2_hs : 7,
n2_hs : 7, n2_ls : 360,
n2_ls : 360, n31 : 63,
n31 : 63, n32 : 63,
n32 : 63, bwsel : 4,
bwsel : 4, crystal_ref: false
crystal_ref: false }
},
si5324::Input::Ckin1
)
}, },
RtioClock::Int_150 => { // 150MHz output, from crystal RtioClock::Int_150 => { // 150MHz output, from crystal
info!("using internal 150MHz RTIO clock"); info!("using internal 150MHz RTIO clock");
( si5324::FrequencySettings {
si5324::FrequencySettings { n1_hs : 9,
n1_hs : 9, nc1_ls : 4,
nc1_ls : 4, n2_hs : 10,
n2_hs : 10, n2_ls : 33732,
n2_ls : 33732, n31 : 7139,
n31 : 7139, n32 : 7139,
n32 : 7139, bwsel : 3,
bwsel : 3, crystal_ref: true
crystal_ref: true }
},
si5324::Input::Ckin2
)
}, },
RtioClock::Int_100 => { // 100MHz output, from crystal. RtioClock::Int_100 => { // 100MHz output, from crystal
info!("using internal 100MHz RTIO clock"); info!("using internal 100MHz RTIO clock");
( si5324::FrequencySettings {
si5324::FrequencySettings { n1_hs : 9,
n1_hs : 9, nc1_ls : 6,
nc1_ls : 6, n2_hs : 10,
n2_hs : 10, n2_ls : 33732,
n2_ls : 33732, n31 : 7139,
n31 : 7139, n32 : 7139,
n32 : 7139, bwsel : 3,
bwsel : 3, crystal_ref: true
crystal_ref: true }
},
si5324::Input::Ckin2
)
}, },
RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
info!("using internal 125MHz RTIO clock"); info!("using internal 125MHz RTIO clock");
( si5324::FrequencySettings {
si5324::FrequencySettings { n1_hs : 10,
n1_hs : 10, nc1_ls : 4,
nc1_ls : 4, n2_hs : 10,
n2_hs : 10, n2_ls : 19972,
n2_ls : 19972, n31 : 4565,
n31 : 4565, n32 : 4565,
n32 : 4565, bwsel : 4,
bwsel : 4, crystal_ref: true
crystal_ref: true }
}, }
si5324::Input::Ckin2 _ => { // 125MHz output like above, default (if chosen option is not supported)
) warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", clk);
}, si5324::FrequencySettings {
_ => { // same setting as Int_125, but fallback to default n1_hs : 10,
warn!("rtio_clock setting '{:?}' is unsupported. Falling back to default internal 125MHz RTIO clock.", clk); nc1_ls : 4,
( n2_hs : 10,
si5324::FrequencySettings { n2_ls : 19972,
n1_hs : 10, n31 : 4565,
nc1_ls : 4, n32 : 4565,
n2_hs : 10, bwsel : 4,
n2_ls : 19972, crystal_ref: true
n31 : 4565, }
n32 : 4565,
bwsel : 4,
crystal_ref: true
},
si5324::Input::Ckin2
)
} }
}; };
si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324"); si5324::setup(i2c, &si5324_settings, SI5324_EXT_INPUT, timer).expect("cannot initialize Si5324");
} }
pub fn init(timer: &mut GlobalTimer, cfg: &Config) { pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
@ -240,9 +223,8 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
#[cfg(has_si5324)] #[cfg(has_si5324)]
{ {
let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() }; let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
let si5324_ext_input = si5324::Input::Ckin1;
match clk { match clk {
RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer).expect("cannot bypass Si5324"), RtioClock::Ext0_Bypass => si5324::bypass(i2c, SI5324_EXT_INPUT, timer).expect("cannot bypass Si5324"),
_ => setup_si5324(i2c, timer, clk), _ => setup_si5324(i2c, timer, clk),
} }
} }