diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index ed26d9a..becaf32 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -301,14 +301,21 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
 
         self.roi_counter = CSRStatus(count_width)
         self.roi_update = CSR()
+        self.pix_y = CSRStatus(res_width)
+
+        self.header_l_size = CSRStatus(3*char_width)
+        self.header_x_size = CSRStatus(3*char_width)
+        self.header_y_size = CSRStatus(3*char_width)
+        self.header_new_line = CSRStatus(3*char_width)
+        
         # # #
         
         cdr = ClockDomainsRenamer("cxp_gtx_rx")
     
-        debug_out = True
+        debug_out = False
 
         if not debug_out:
-            self.submodules.pixel_pipeline = pixel_pipeline = cdr(Pixel_Pipeline(res_width, count_width))
+            self.submodules.pixel_pipeline = pixel_pipeline = cdr(Pixel_Pipeline(res_width, count_width, packet_size))
 
             # RTIO interface
 
@@ -330,16 +337,57 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
 
             sentinel = 2**count_width
             count_sys = Signal.like(roi_out.count)
-            # count_rx = Signal.like(roi_out.count)
-            # self.sync.cxp_gtx_rx += count_rx.eq(roi_out.count),
-            # self.specials += MultiReg(count_rx, count_sys),
-         
+
             self.specials += MultiReg(roi_out.count, count_sys),
             self.sync.rio += [
+                # TODO: add gating
                 self.gate_data.i.stb.eq(update),
                 self.gate_data.i.data.eq(count_sys),
             ]
 
+            
+
+            # TODO: fix count_sys seems like end of frame is broken
+            # BUG: it maybe related to the KCode bug that only happens after frameheader decoder COPY (i.e. when sending pixel data)
+            # DEBUG:
+
+            new_line_cnt_rx, new_line_cnt_sys = Signal(3*char_width), Signal(3*char_width)
+            l_size_rx, l_size_sys = Signal(3*char_width), Signal(3*char_width)
+            x_size_rx, x_size_sys = Signal(3*char_width), Signal(3*char_width)
+            y_size_rx, y_size_sys = Signal(3*char_width), Signal(3*char_width)
+            y_pix_rx, y_pix_sys = Signal(res_width), Signal(res_width)
+            self.sync.cxp_gtx_rx += [
+                If(pixel_pipeline.header_decoder.new_line,
+                    new_line_cnt_rx.eq(new_line_cnt_rx + 1),
+                ),
+
+                l_size_rx.eq(pixel_pipeline.header_decoder.metadata.l_size),
+                x_size_rx.eq(pixel_pipeline.header_decoder.metadata.x_size),
+                y_size_rx.eq(pixel_pipeline.header_decoder.metadata.y_size),                
+
+                y_pix_rx.eq(pixel_pipeline.parser.pixel4x[0].y),
+            ]
+            self.specials += [
+                MultiReg(new_line_cnt_rx, new_line_cnt_sys),
+                MultiReg(l_size_rx, l_size_sys),
+                MultiReg(x_size_rx, x_size_sys),
+                MultiReg(y_size_rx, y_size_sys),
+                MultiReg(y_pix_rx, y_pix_sys),
+            ]
+            self.sync += [
+                self.header_new_line.status.eq(new_line_cnt_sys),
+                self.pix_y.status.eq(y_pix_sys),
+                self.header_l_size.status.eq(l_size_sys),
+                self.header_x_size.status.eq(x_size_sys),
+                self.header_y_size.status.eq(y_size_sys),
+                self.roi_counter.status.eq(count_sys),
+                If(update,
+                    self.roi_update.w.eq(1),
+                ).Elif(self.roi_update.re,
+                    self.roi_update.w.eq(0),
+                ),
+            ]
+
         else:
             # DEBUG:
             crc_checker = cdr(CXPCRC32_Checker())
@@ -378,8 +426,17 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
 
         # Connect pipeline
         for i, p in enumerate(pipelines):
-            # Assume downconns pipeline already marks the eop
-            self.comb += p.rx.source.connect(arbiter.sinks[i])
+            # DEBUG:
+            test_fifo = cdr(stream.SyncFIFO(word_layout_dchar, 32, True))
+            self.submodules += test_fifo
+            self.comb += [
+                p.rx.source.connect(test_fifo.sink),
+                test_fifo.source.connect(arbiter.sinks[i])
+                
+            ]
+
+            # # Assume downconns pipeline already marks the eop
+            # self.comb += p.rx.source.connect(arbiter.sinks[i])
 
         self.comb += arbiter.source.connect(broadcaster.sink)