diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index 61a7787..c292229 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -249,11 +249,8 @@ class TX_Command_Packet(Module, AutoCSR):
 
         # # #
 
-        # TODO: use RAM instead of FIFO ?
         # Section 12.1.2 (CXP-001-2021)
         # Max control packet size is 128 bytes
-        
-        # NOTE: The firmware will lock up if there is not enough space for the packet
         self.submodules.fifo = fifo = stream.SyncFIFO(layout, 128)
         self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
         self.source = pak_wrp.source