forked from M-Labs/artiq-zynq
master wrpll: remove nested mmcm module
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7300ecce25
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5aade6abb2
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@ -552,10 +552,6 @@ pub mod wrpll {
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pub mod sma_pll {
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pub mod sma_pll {
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use super::*;
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use super::*;
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mod mmcm {
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use super::*;
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pub struct MmcmSetting {
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pub struct MmcmSetting {
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pub clkout0_reg1: u16, //0x08
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pub clkout0_reg1: u16, //0x08
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pub clkout0_reg2: u16, //0x09
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pub clkout0_reg2: u16, //0x09
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@ -613,7 +609,7 @@ pub mod sma_pll {
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unsafe { csr::sma_pll::drp_ready_read() == 1 }
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unsafe { csr::sma_pll::drp_ready_read() == 1 }
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}
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}
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pub fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
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fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
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set_addr(address);
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set_addr(address);
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set_enable(true);
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set_enable(true);
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// Set DADDR on the MMCM and assert DEN for one clock cycle
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// Set DADDR on the MMCM and assert DEN for one clock cycle
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@ -627,7 +623,7 @@ pub mod sma_pll {
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get_data()
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get_data()
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}
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}
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pub fn write(timer: &mut GlobalTimer, address: u8, value: u16) {
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fn write(timer: &mut GlobalTimer, address: u8, value: u16) {
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set_addr(address);
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set_addr(address);
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set_data(value);
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set_data(value);
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set_write_enable(true);
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set_write_enable(true);
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@ -643,7 +639,7 @@ pub mod sma_pll {
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}
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}
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}
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}
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pub fn reset(rst: bool) {
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fn reset(rst: bool) {
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unsafe {
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unsafe {
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let val = if rst { 1 } else { 0 };
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let val = if rst { 1 } else { 0 };
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csr::sma_pll::mmcm_reset_write(val)
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csr::sma_pll::mmcm_reset_write(val)
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@ -677,7 +673,6 @@ pub mod sma_pll {
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}
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}
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Ok(())
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Ok(())
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}
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}
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}
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pub fn setup(timer: &mut GlobalTimer) {
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pub fn setup(timer: &mut GlobalTimer) {
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for addr in 7..12 {
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for addr in 7..12 {
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