forked from M-Labs/artiq-zynq
master wrpll: remove nested mmcm module
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7300ecce25
commit
5aade6abb2
@ -552,131 +552,126 @@ pub mod wrpll {
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pub mod sma_pll {
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use super::*;
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mod mmcm {
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pub struct MmcmSetting {
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pub clkout0_reg1: u16, //0x08
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pub clkout0_reg2: u16, //0x09
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pub clkfbout_reg1: u16, //0x14
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pub clkfbout_reg2: u16, //0x15
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pub div_reg: u16, //0x16
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pub lock_reg1: u16, //0x18
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pub lock_reg2: u16, //0x19
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pub lock_reg3: u16, //0x1A
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pub power_reg: u16, //0x28
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pub filt_reg1: u16, //0x4E
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pub filt_reg2: u16, //0x4F
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}
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use super::*;
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pub struct MmcmSetting {
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pub clkout0_reg1: u16, //0x08
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pub clkout0_reg2: u16, //0x09
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pub clkfbout_reg1: u16, //0x14
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pub clkfbout_reg2: u16, //0x15
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pub div_reg: u16, //0x16
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pub lock_reg1: u16, //0x18
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pub lock_reg2: u16, //0x19
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pub lock_reg3: u16, //0x1A
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pub power_reg: u16, //0x28
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pub filt_reg1: u16, //0x4E
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pub filt_reg2: u16, //0x4F
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fn one_clock_cycle(timer: &mut GlobalTimer) {
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unsafe {
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csr::sma_pll::drp_clk_write(1);
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timer.delay_us(1);
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csr::sma_pll::drp_clk_write(0);
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timer.delay_us(1);
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}
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}
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fn one_clock_cycle(timer: &mut GlobalTimer) {
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unsafe {
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csr::sma_pll::drp_clk_write(1);
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timer.delay_us(1);
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csr::sma_pll::drp_clk_write(0);
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timer.delay_us(1);
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}
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fn set_addr(address: u8) {
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unsafe {
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csr::sma_pll::drp_addr_write(address);
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}
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}
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fn set_addr(address: u8) {
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unsafe {
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csr::sma_pll::drp_addr_write(address);
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}
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fn set_data(value: u16) {
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unsafe {
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csr::sma_pll::drp_in_write(value);
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}
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}
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fn set_data(value: u16) {
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unsafe {
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csr::sma_pll::drp_in_write(value);
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}
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fn set_enable(en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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csr::sma_pll::drp_en_write(val);
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}
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}
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fn set_enable(en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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csr::sma_pll::drp_en_write(val);
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}
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fn set_write_enable(en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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csr::sma_pll::drp_w_en_write(val);
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}
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}
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fn set_write_enable(en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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csr::sma_pll::drp_w_en_write(val);
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}
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}
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fn get_data() -> u16 {
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unsafe { csr::sma_pll::drp_out_read() }
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}
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fn get_data() -> u16 {
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unsafe { csr::sma_pll::drp_out_read() }
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}
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fn drp_ready() -> bool {
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unsafe { csr::sma_pll::drp_ready_read() == 1 }
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}
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fn drp_ready() -> bool {
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unsafe { csr::sma_pll::drp_ready_read() == 1 }
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}
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fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
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set_addr(address);
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set_enable(true);
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// Set DADDR on the MMCM and assert DEN for one clock cycle
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one_clock_cycle(timer);
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pub fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
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set_addr(address);
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set_enable(true);
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// Set DADDR on the MMCM and assert DEN for one clock cycle
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set_enable(false);
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while !drp_ready() {
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// keep the clock signal until data is ready
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one_clock_cycle(timer);
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set_enable(false);
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while !drp_ready() {
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// keep the clock signal until data is ready
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one_clock_cycle(timer);
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}
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get_data()
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}
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get_data()
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}
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pub fn write(timer: &mut GlobalTimer, address: u8, value: u16) {
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set_addr(address);
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set_data(value);
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set_write_enable(true);
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set_enable(true);
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// Set DADDR, DI on the MMCM and assert DWE, DEN for one clock cycle
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fn write(timer: &mut GlobalTimer, address: u8, value: u16) {
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set_addr(address);
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set_data(value);
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set_write_enable(true);
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set_enable(true);
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// Set DADDR, DI on the MMCM and assert DWE, DEN for one clock cycle
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one_clock_cycle(timer);
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set_write_enable(false);
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set_enable(false);
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while !drp_ready() {
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// keep the clock signal until write is finished
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one_clock_cycle(timer);
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set_write_enable(false);
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set_enable(false);
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while !drp_ready() {
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// keep the clock signal until write is finished
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one_clock_cycle(timer);
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}
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}
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}
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pub fn reset(rst: bool) {
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unsafe {
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let val = if rst { 1 } else { 0 };
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csr::sma_pll::mmcm_reset_write(val)
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}
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fn reset(rst: bool) {
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unsafe {
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let val = if rst { 1 } else { 0 };
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csr::sma_pll::mmcm_reset_write(val)
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}
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}
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pub fn setup(timer: &mut GlobalTimer, settings: MmcmSetting) -> Result<(), &'static str> {
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// Based on "DRP State Machine" from XAPP888
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pub fn setup(timer: &mut GlobalTimer, settings: MmcmSetting) -> Result<(), &'static str> {
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// Based on "DRP State Machine" from XAPP888
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// hold reset HIGH during mmcm config
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reset(true);
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write(timer, 0x08, settings.clkout0_reg1);
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write(timer, 0x09, settings.clkout0_reg2);
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write(timer, 0x14, settings.clkfbout_reg1);
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write(timer, 0x15, settings.clkfbout_reg2);
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write(timer, 0x16, settings.div_reg);
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write(timer, 0x18, settings.lock_reg1);
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write(timer, 0x19, settings.lock_reg2);
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write(timer, 0x1A, settings.lock_reg3);
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write(timer, 0x28, settings.power_reg);
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write(timer, 0x4E, settings.filt_reg1);
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write(timer, 0x4F, settings.filt_reg2);
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reset(false);
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// hold reset HIGH during mmcm config
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reset(true);
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write(timer, 0x08, settings.clkout0_reg1);
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write(timer, 0x09, settings.clkout0_reg2);
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write(timer, 0x14, settings.clkfbout_reg1);
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write(timer, 0x15, settings.clkfbout_reg2);
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write(timer, 0x16, settings.div_reg);
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write(timer, 0x18, settings.lock_reg1);
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write(timer, 0x19, settings.lock_reg2);
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write(timer, 0x1A, settings.lock_reg3);
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write(timer, 0x28, settings.power_reg);
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write(timer, 0x4E, settings.filt_reg1);
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write(timer, 0x4F, settings.filt_reg2);
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reset(false);
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// wait for the mmcm to lock
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timer.delay_us(100);
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// wait for the mmcm to lock
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timer.delay_us(100);
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let locked = unsafe { csr::sma_pll::mmcm_locked_read() == 1 };
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if !locked {
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return Err("failed to generate 125Mhz ref clock from SMA CLKIN");
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}
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Ok(())
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let locked = unsafe { csr::sma_pll::mmcm_locked_read() == 1 };
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if !locked {
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return Err("failed to generate 125Mhz ref clock from SMA CLKIN");
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}
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Ok(())
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}
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pub fn setup(timer: &mut GlobalTimer) {
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