forked from M-Labs/artiq-zynq
cxp downconn: fix tx reset & cleanup
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parent
e0369d2eb2
commit
5a40422f1d
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@ -32,10 +32,10 @@ class CXP_DownConn(Module, AutoCSR):
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# # #
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self.submodules.qpll = QPLL(refclk, sys_clk_freq)
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self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
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# single & master tx_mode can lock with rx in loopback
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self.submodules.gtx = GTX(self.qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
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self.submodules.gtx = gtx = GTX(self.qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
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# TEST: txusrclk alignment
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# 1) use GTREFCLK with TXSYSCLKSEL = 0b10 -> still inconsistant
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@ -44,26 +44,28 @@ class CXP_DownConn(Module, AutoCSR):
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self.sync += [
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# PLL
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self.qpll.reset.eq(self.qpll_reset.re),
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self.qpll_locked.status.eq(self.qpll.lock),
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qpll.reset.eq(self.qpll_reset.re),
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self.qpll_locked.status.eq(qpll.lock),
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# GTX
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self.txinit_phaligndone.status.eq(self.gtx.tx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(self.gtx.rx_init.Xxphaligndone),
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self.rx_ready.status.eq(self.gtx.rx_ready),
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self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
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self.rx_ready.status.eq(gtx.rx_ready),
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self.gtx.txenable.eq(self.txenable.storage[0]),
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self.gtx.tx_restart.eq(self.tx_restart.re),
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self.gtx.rx_restart.eq(self.rx_restart.storage),
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self.gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
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self.gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
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# self.gtx.rx_alignment_en.eq(self.rx_data_alignment.storage),
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gtx.txenable.eq(self.txenable.storage[0]),
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gtx.tx_restart.eq(self.tx_restart.re),
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gtx.rx_restart.eq(self.rx_restart.storage),
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gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
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gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
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# gtx.rx_alignment_en.eq(self.rx_data_alignment.storage),
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# GTX DRP
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self.gtx.tx_rate.eq(self.tx_div.storage),
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self.gtx.rx_rate.eq(self.rx_div.storage),
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gtx.tx_rate.eq(self.tx_div.storage),
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gtx.rx_rate.eq(self.rx_div.storage),
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]
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# DEBUG: txusrclk PLL DRG
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self.txpll_reset = CSRStorage()
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self.pll_daddr = CSRStorage(7)
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self.pll_dclk = CSRStorage()
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@ -76,32 +78,32 @@ class CXP_DownConn(Module, AutoCSR):
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self.pll_dready = CSRStatus()
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self.comb += [
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self.gtx.txpll_reset.eq(self.txpll_reset.storage),
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self.gtx.pll_daddr.eq(self.pll_daddr.storage),
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self.gtx.pll_dclk.eq(self.pll_dclk.storage),
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self.gtx.pll_den.eq(self.pll_den.storage),
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self.gtx.pll_din.eq(self.pll_din.storage),
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self.gtx.pll_dwen.eq(self.pll_dwen.storage),
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gtx.txpll_reset.eq(self.txpll_reset.storage),
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gtx.pll_daddr.eq(self.pll_daddr.storage),
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gtx.pll_dclk.eq(self.pll_dclk.storage),
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gtx.pll_den.eq(self.pll_den.storage),
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gtx.pll_din.eq(self.pll_din.storage),
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gtx.pll_dwen.eq(self.pll_dwen.storage),
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self.txpll_locked.status.eq(self.gtx.txpll_locked),
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self.pll_dout.status.eq(self.gtx.pll_dout),
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self.pll_dready.status.eq(self.gtx.pll_dready),
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self.txpll_locked.status.eq(gtx.txpll_locked),
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self.pll_dout.status.eq(gtx.pll_dout),
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self.pll_dready.status.eq(gtx.pll_dready),
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]
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# DEBUG:loopback
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self.loopback_mode = CSRStorage(3)
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self.comb += self.gtx.loopback_mode.eq(self.loopback_mode.storage)
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self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage)
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# DEBUG:SMA
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# DEBUG: IO SMA & PMOD
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self.specials += [
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Instance("OBUF", i_I=self.gtx.rxoutclk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=self.gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# pmod 0-7 pin
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Instance("OBUF", i_I=self.qpll.lock, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=self.qpll.reset, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=self.gtx.tx_init.gtXxreset, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=gtx.tx_init.gtXxreset, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.tx_init.Xxdlysreset, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=gtx.tx_init.Xxdlysresetdone , o_O=pmod_pads[2]),
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Instance("OBUF", i_I=gtx.tx_init.Xxphaligndone , o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[6]),
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@ -397,11 +399,10 @@ class GTX(Module):
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# # #
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# TX generates cxp_tx clock, init must be in system domain
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self.submodules.tx_init = tx_init = GTXInit(sys_clk_freq, False, mode=tx_mode)
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# RX receives restart commands from RTIO domain
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# DEBUG: 500e6 is used to fix tx reset by holding gtxtxreset for a couple cycle more
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self.submodules.tx_init = tx_init = GTXInit(500e6, False, mode=tx_mode)
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# RX receives restart commands from txusrclk domain
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self.submodules.rx_init = rx_init = ClockDomainsRenamer("cxp_gtx_tx")(GTXInit(qpll.tx_usrclk_freq, True, mode=rx_mode))
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# DEBUG: change back to cxp_gtx_tx once QPLL works
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# self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode)
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self.comb += [
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tx_init.cplllock.eq(qpll.lock),
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