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pipeline GW: refactor to add packet type into mem

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morgan 2025-01-23 12:09:57 +08:00
parent aed4e2fa25
commit 59971fa996
1 changed files with 28 additions and 18 deletions
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46
src/gateware/cxp_pipeline.py
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@ -386,19 +386,31 @@ class Control_Packet_Reader(Module):
self.sink = stream.Endpoint(word_layout_dchar) self.sink = stream.Endpoint(word_layout_dchar)
self.source = stream.Endpoint(word_layout_dchar) self.source = stream.Endpoint(word_layout_dchar)
# N buffers for firmware to read packet from
self.specials.mem = mem = Memory(word_width, nslot*buffer_depth)
self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
# Data packet parser
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
addr_nbits = log2_int(buffer_depth)
addr = Signal(addr_nbits)
cnt = Signal(max=0x100)
fsm.act("IDLE", fsm.act("IDLE",
NextValue(addr, addr.reset),
NextValue(cnt, cnt.reset),
self.sink.ack.eq(1), self.sink.ack.eq(1),
If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)), If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)),
NextState("DECODE"), NextState("DECODE"),
) )
) )
cnt = Signal(max=0x100)
addr_nbits = log2_int(buffer_depth)
addr = Signal(addr_nbits)
test_pak = Signal() test_pak = Signal()
buf_mem_we = Signal.like(mem_port.we)
buf_mem_dat_w = Signal.like(mem_port.dat_w)
buf_mem_adr = Signal.like(mem_port.adr)
fsm.act("DECODE", fsm.act("DECODE",
self.sink.ack.eq(1), self.sink.ack.eq(1),
If(self.sink.stb, If(self.sink.stb,
@ -406,22 +418,24 @@ class Control_Packet_Reader(Module):
type["data_stream"]: NextState("STREAMING"), type["data_stream"]: NextState("STREAMING"),
type["test_packet"]: [ type["test_packet"]: [
test_pak.eq(1), test_pak.eq(1),
NextValue(cnt, cnt.reset),
NextState("VERIFY_TEST_PATTERN"), NextState("VERIFY_TEST_PATTERN"),
], ],
type["control_ack_no_tag"]:[ type["control_ack_no_tag"]:[
NextValue(self.packet_type, self.sink.dchar), buf_mem_we.eq(1),
NextValue(addr, addr.reset), buf_mem_dat_w.eq(self.sink.data),
NextValue(addr, addr + 1),
NextState("LOAD_BUFFER"), NextState("LOAD_BUFFER"),
], ],
type["control_ack_with_tag"]:[ type["control_ack_with_tag"]:[
NextValue(self.packet_type, self.sink.dchar), buf_mem_we.eq(1),
NextValue(addr, addr.reset), buf_mem_dat_w.eq(self.sink.data),
NextValue(addr, addr + 1),
NextState("LOAD_BUFFER"), NextState("LOAD_BUFFER"),
], ],
type["event"]: [ type["event"]: [
NextValue(self.packet_type, self.sink.dchar), buf_mem_we.eq(1),
NextValue(addr, addr.reset), buf_mem_dat_w.eq(self.sink.data),
NextValue(addr, addr + 1),
NextState("LOAD_BUFFER"), NextState("LOAD_BUFFER"),
], ],
type["heartbeat"] : [ type["heartbeat"] : [
@ -436,7 +450,8 @@ class Control_Packet_Reader(Module):
}), }),
) )
) )
# For stream data packet
# copy stream data packet with pak_end Kcode
fsm.act("STREAMING", fsm.act("STREAMING",
self.sink.connect(self.source), self.sink.connect(self.source),
# assume downstream is not blocked # assume downstream is not blocked
@ -476,6 +491,7 @@ class Control_Packet_Reader(Module):
) )
# TODO: move this out of this module
self.sync += [ self.sync += [
If(self.test_cnt_reset, If(self.test_cnt_reset,
self.test_err_cnt.eq(self.test_err_cnt.reset), self.test_err_cnt.eq(self.test_err_cnt.reset),
@ -489,20 +505,14 @@ class Control_Packet_Reader(Module):
) )
] ]
# N buffers for firmware to read packet from
self.specials.mem = mem = Memory(word_width, nslot*buffer_depth)
self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
# buffered mem_port to improve timing # buffered mem_port to improve timing
buf_mem_we = Signal.like(mem_port.we)
buf_mem_dat_w = Signal.like(mem_port.dat_w)
buf_mem_adr = Signal.like(mem_port.adr)
self.sync += [ self.sync += [
mem_port.we.eq(buf_mem_we), mem_port.we.eq(buf_mem_we),
mem_port.dat_w.eq(buf_mem_dat_w), mem_port.dat_w.eq(buf_mem_dat_w),
mem_port.adr.eq(buf_mem_adr) mem_port.adr.eq(buf_mem_adr)
] ]
# TODO: move write_ptr_sys out of this module
write_ptr = Signal(log2_int(nslot)) write_ptr = Signal(log2_int(nslot))
self.write_ptr_sys = Signal.like(write_ptr) self.write_ptr_sys = Signal.like(write_ptr)
self.specials += MultiReg(write_ptr, self.write_ptr_sys), self.specials += MultiReg(write_ptr, self.write_ptr_sys),