From 59971fa996189e5b349ef2c0715e8c507b3e7e19 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Thu, 23 Jan 2025 12:09:57 +0800
Subject: [PATCH] pipeline GW: refactor to add packet type into mem

---
 src/gateware/cxp_pipeline.py | 46 ++++++++++++++++++++++--------------
 1 file changed, 28 insertions(+), 18 deletions(-)

diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index 10a8a95..e07dc06 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -386,19 +386,31 @@ class Control_Packet_Reader(Module):
         self.sink = stream.Endpoint(word_layout_dchar)
         self.source = stream.Endpoint(word_layout_dchar)
 
+        # N buffers for firmware to read packet from
+        self.specials.mem = mem = Memory(word_width, nslot*buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
+
+
+        # Data packet parser
+        
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
 
+        addr_nbits = log2_int(buffer_depth)
+        addr = Signal(addr_nbits)
+        cnt = Signal(max=0x100)
         fsm.act("IDLE",
+            NextValue(addr, addr.reset),
+            NextValue(cnt, cnt.reset),
             self.sink.ack.eq(1),
             If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)),
                 NextState("DECODE"),
             )
         )
 
-        cnt = Signal(max=0x100)
-        addr_nbits = log2_int(buffer_depth)
-        addr = Signal(addr_nbits)
         test_pak = Signal()
+        buf_mem_we = Signal.like(mem_port.we)
+        buf_mem_dat_w = Signal.like(mem_port.dat_w)
+        buf_mem_adr = Signal.like(mem_port.adr)
         fsm.act("DECODE",
             self.sink.ack.eq(1),
             If(self.sink.stb,
@@ -406,22 +418,24 @@ class Control_Packet_Reader(Module):
                     type["data_stream"]: NextState("STREAMING"),
                     type["test_packet"]: [
                         test_pak.eq(1),
-                        NextValue(cnt, cnt.reset),
                         NextState("VERIFY_TEST_PATTERN"),
                     ],
                     type["control_ack_no_tag"]:[
-                        NextValue(self.packet_type, self.sink.dchar),
-                        NextValue(addr, addr.reset),
+                        buf_mem_we.eq(1),
+                        buf_mem_dat_w.eq(self.sink.data),
+                        NextValue(addr, addr + 1),
                         NextState("LOAD_BUFFER"),
                     ],
                     type["control_ack_with_tag"]:[
-                        NextValue(self.packet_type, self.sink.dchar),
-                        NextValue(addr, addr.reset),
+                        buf_mem_we.eq(1),
+                        buf_mem_dat_w.eq(self.sink.data),
+                        NextValue(addr, addr + 1),
                         NextState("LOAD_BUFFER"),
                     ],
                     type["event"]: [
-                        NextValue(self.packet_type, self.sink.dchar),
-                        NextValue(addr, addr.reset),
+                        buf_mem_we.eq(1),
+                        buf_mem_dat_w.eq(self.sink.data),
+                        NextValue(addr, addr + 1),
                         NextState("LOAD_BUFFER"),
                     ],
                     type["heartbeat"] : [
@@ -436,7 +450,8 @@ class Control_Packet_Reader(Module):
                 }),
             )
         )
-        # For stream data packet
+
+        # copy stream data packet with pak_end Kcode
         fsm.act("STREAMING",
             self.sink.connect(self.source),
             # assume downstream is not blocked
@@ -476,6 +491,7 @@ class Control_Packet_Reader(Module):
                 
         )
 
+        # TODO: move this out of this module
         self.sync += [
             If(self.test_cnt_reset,
                 self.test_err_cnt.eq(self.test_err_cnt.reset),
@@ -489,20 +505,14 @@ class Control_Packet_Reader(Module):
             )
         ]
 
-        # N buffers for firmware to read packet from
-        self.specials.mem = mem = Memory(word_width, nslot*buffer_depth)
-        self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
-
         # buffered mem_port to improve timing
-        buf_mem_we = Signal.like(mem_port.we)
-        buf_mem_dat_w = Signal.like(mem_port.dat_w)
-        buf_mem_adr = Signal.like(mem_port.adr)
         self.sync += [
             mem_port.we.eq(buf_mem_we),
             mem_port.dat_w.eq(buf_mem_dat_w),
             mem_port.adr.eq(buf_mem_adr)
         ]
 
+        # TODO: move write_ptr_sys out of this module
         write_ptr = Signal(log2_int(nslot))
         self.write_ptr_sys = Signal.like(write_ptr)
         self.specials += MultiReg(write_ptr, self.write_ptr_sys),