forked from M-Labs/artiq-zynq
zc706: add CXP_DEMO variant
zc706: add fmc pads zc706: add constraint to fix comma alignment & setup/hold time issue zc706: add csr & mem group for cxp zc706: add CXP to rtio_channel
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1a3ac9763d
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577fa03b78
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@ -25,6 +25,8 @@ import analyzer
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import acpki
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import drtio_aux_controller
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import zynq_clocking
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import cxp_4r_fmc
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import cxp
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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class SMAClkinForward(Module):
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@ -138,7 +140,7 @@ class ZC706(SoCCore):
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platform.add_extension(si5324_fmc33)
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self.comb += platform.request("si5324_33").rst_n.eq(1)
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cdr_clk = Signal()
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self.cdr_clk = Signal()
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cdr_clk_buf = Signal()
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si5324_out = platform.request("si5324_clkout")
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platform.add_period_constraint(si5324_out.p, 8.0)
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@ -146,11 +148,11 @@ class ZC706(SoCCore):
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Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=si5324_out.p, i_IB=si5324_out.n,
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o_O=cdr_clk,
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o_O=self.cdr_clk,
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p_CLKCM_CFG="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKSWING_CFG=3),
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Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
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Instance("BUFG", i_I=self.cdr_clk, o_O=cdr_clk_buf)
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]
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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@ -652,6 +654,129 @@ class _NIST_QC2_RTIO:
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self.add_rtio(rtio_channels)
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class CXP_FMC():
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"""
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CoaXpress FMC with 4 CXP channel and 1 SMA trigger
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"""
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def __init__(self):
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platform = self.platform
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platform.add_extension(cxp_4r_fmc.fmc_adapter_io)
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platform.add_extension(leds_fmc33)
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debug_sma = [
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("user_sma_clock_33", 0,
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Subsignal("p_tx", Pins("AD18"), IOStandard("LVCMOS33")),
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Subsignal("n_rx", Pins("AD19"), IOStandard("LVCMOS33")),
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),
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]
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pmod1_33 = [
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("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")),
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("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
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("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
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("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
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("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")),
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("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")),
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("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")),
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("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")),
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]
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platform.add_extension(debug_sma)
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platform.add_extension(pmod1_33)
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debug_sma_pad = platform.request("user_sma_clock_33")
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pmod_pads = [platform.request("pmod1_33", i) for i in range(8)]
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clk_freq = 125e6
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links = 1
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cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
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cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
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self.submodules.cxp_phys = cxp_phys = cxp.CXP_PHYS(
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refclk=self.cdr_clk,
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upconn_pads=cxp_upconn_pads,
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downconn_pads=cxp_downconn_pads,
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sys_clk_freq=clk_freq,
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debug_sma=debug_sma_pad,
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pmod_pads = pmod_pads
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)
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self.csr_devices.append("cxp_phys")
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rtio_channels = []
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cxp_csr_group = []
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cxp_tx_mem_group = []
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cxp_rx_mem_group = []
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cxp_loopback_mem_group = []
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for i, (tx, rx) in enumerate(zip(cxp_phys.upconn.tx_phys, cxp_phys.downconn.rx_phys)):
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cxp_name = "cxp" + str(i)
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cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
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if i == 0:
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cxp_interface = cdr(cxp.CXP_Master(tx, rx, debug_sma_pad, pmod_pads))
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# Add rtlink for Master Connection only
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print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
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rtio_channels.append(rtio.Channel.from_phy(cxp_interface))
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else:
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cxp_interface = cdr(cxp.CXP_Extension(tx, rx, debug_sma_pad, pmod_pads))
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setattr(self.submodules, cxp_name, cxp_interface)
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self.csr_devices.append(cxp_name)
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cxp_csr_group.append(cxp_name)
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# Add memory group
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rx_mem_name = "cxp_rx" + str(i) + "_mem"
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rx_mem_size = cxp_interface.get_rx_mem_size()
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cxp_rx_mem_group.append(rx_mem_name)
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memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), rx_mem_size)
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self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, rx_mem_size)
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tx_mem_name = "cxp_tx" + str(i) + "_mem"
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tx_mem_size = cxp_interface.get_tx_mem_size()
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cxp_tx_mem_group.append(tx_mem_name)
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memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), tx_mem_size)
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self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, tx_mem_size)
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# DEBUG loopback tx memory
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loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem"
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loopback_mem_size = cxp_interface.get_loopback_tx_mem_size()
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cxp_loopback_mem_group.append(loopback_mem_name)
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memory_address = self.axi2csr.register_port(cxp_interface.get_loopback_tx_port(), loopback_mem_size)
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self.add_memory_region(loopback_mem_name, self.mem_map["csr"] + memory_address, loopback_mem_size)
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self.add_memory_group("cxp_tx_mem", cxp_tx_mem_group)
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self.add_memory_group("cxp_rx_mem", cxp_rx_mem_group)
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self.add_memory_group("cxp_loopback_mem", cxp_loopback_mem_group)
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self.add_csr_group("cxp", cxp_csr_group)
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# max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
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# zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
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# pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
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for rx in cxp_phys.downconn.rx_phys :
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platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2)
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platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2)
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# constraint the CLK path
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platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_tx.clk, rx.gtx.cd_cxp_gtx_rx.clk)
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# FIXME remove this placeholder RTIO channel
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# There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)
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# see https://github.com/m-labs/artiq/pull/2158 for similar issue
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print("USER LED at RTIO channel 0x{:06x}".format(len(rtio_channels)))
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phy = ttl_simple.Output(self.platform.request("user_led_33", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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rtio_channels.append(rtio.LogChannel())
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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self.add_rtio(rtio_channels)
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
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def __init__(self, acpki, drtio100mhz):
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ZC706.__init__(self, acpki)
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@ -684,8 +809,13 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
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_SatelliteBase.__init__(self, acpki, drtio100mhz)
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_NIST_QC2_RTIO.__init__(self)
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class CXP_Demo(ZC706, CXP_FMC):
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def __init__(self, acpki, drtio100mhz):
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ZC706.__init__(self, acpki)
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CXP_FMC.__init__(self)
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite, CXP_Demo]}
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def main():
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parser = argparse.ArgumentParser(
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