From 553942232dcb9094270b2422195066ab65e81284 Mon Sep 17 00:00:00 2001 From: morgan Date: Tue, 28 Jan 2025 17:47:59 +0800 Subject: [PATCH] temp: update notes temp: add build gw script temp: update notes --- build_gw.sh | 4 ++++ cxp_note.md | 47 +++++++++++++++++++++++++++++------------------ 2 files changed, 33 insertions(+), 18 deletions(-) create mode 100755 build_gw.sh diff --git a/build_gw.sh b/build_gw.sh new file mode 100755 index 0000000..8405437 --- /dev/null +++ b/build_gw.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -e + +python src/gateware/zc706.py -r build/pl.rs -c build/rustc-cfg -m build/mem.rs -V CXP_Demo -g build/gateware/ diff --git a/cxp_note.md b/cxp_note.md index b88a59d..b7ffd91 100644 --- a/cxp_note.md +++ b/cxp_note.md @@ -24,6 +24,7 @@ [x] follow DRTIO DMA [x] check crc [x] GTX Multilane setup + [x] add tx/rx mode for gtx - Camera boostrap [x] get the CXP version [x] test connection @@ -32,6 +33,11 @@ - Camera frame pipeline [x] CXP frame packet routing (maybe no need to routing non zero streaming id (we have ROI buildin anyways)?) [x] CXP CRC32 detection + [x] Region of interest engine (32 bits mode) + [x] pixel gearbox + [x] pixel parser (xy pos) + [x] Test out CXP trigger + [x] 8, 10, 12 bits in white test image mode ## TODO @@ -39,37 +45,42 @@ [] flake.nix mod [] local_run.sh mod ### Gateware -[x] rename word_dw to word_width -[x] Test out CXP trigger -[] add __init__.py for cxp?? +[x] refactor error_cnt +[x] Heartbeat (is it useful?? lol) +[x] rename circular buffer to slots +[x] use `from misoc.interconnect.stream import Endpoint` instead +[x] add __init__.py for cxp?? [] Try to fix tight s/h time pins -[] refactor error_cnt -[] Heartbeat (is it useful?? lol) -[] rename circular buffer to slots +[] remove self.source.ack in fsm + - seems to kill timing :V +[] multilane ROI + [] Region of interest engine (n*32 bits mode) + [] bus widener + fifo [] remove pmod/debug_sma in fns args -[] add enum for gtx mode (e.g. tx only, rx only, both) - [] use if tx_mode / rx_mode instead -[] Region of interest engine - [x] pixel gearbox - [] pixel parser (xy pos) [] rtio to getting the frame - O: trigger - I: frame -[] add a packet parser module that mux the packet? ### Firmware (design with driver) -[] Camera linkdown detection +[x] API programming +[x] add tag handling for api calls + - support lane reset in kernel using syscall +[] double check cfg gating + [] add libboard_artiq/src/lib.rs cfg gating [] Camera auto linkup/linkdown using threads -[] API programming -[] add tag handling for api calls - - support line reset in kernel using syscall -[] add heartbeat checking + [] Camera linkdown detection + [] add mutex support for tx/rx camera programming (or block them when camera is not ready) + [] add xml url printout in uart (so user can just download the xml using api) + [] add heartbeat checking +[] add flashing LED (non-essential) +[] add PoCXP (non-essential) ### Coredevice Driver +[x] use camera test pattern black/white to verify roi https://docs.baslerweb.com/test-patterns +[x] test out 8/10/12 bit mode [] support simple camera programming interface (Not real time) - basic i2c-like interface with read/write u32 [] add grabber like fns & docs -[] use camera test pattern black/white to verify roi https://docs.baslerweb.com/test-patterns ### PR