forked from M-Labs/artiq-zynq
downconn GW: rename variable
downconn GW: remove csr downconn GW: clenaup
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7eeceb1dfa
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5414730baa
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@ -7,29 +7,20 @@ from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.interconnect import stream
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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from cxp_pipeline import downconn_layout
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from cxp_pipeline import word_layout
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from functools import reduce
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from functools import reduce
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from operator import add
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from operator import add
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class CXP_DownConn_PHY(Module, AutoCSR):
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class CXP_DownConn_PHYS(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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nconn = len(pads)
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self.rx_start_init = CSRStorage()
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self.rx_restart = CSR()
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self.tx_start_init = CSRStorage()
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self.tx_restart = CSR()
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self.txenable = CSRStorage()
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self.rx_ready = CSRStatus(nconn)
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self.qpll_reset = CSR()
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self.qpll_reset = CSR()
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self.qpll_locked = CSRStatus()
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self.qpll_locked = CSRStatus()
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self.gtxs = []
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self.rx_phys = []
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# # #
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# # #
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# For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL
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self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
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self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
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self.sync += [
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self.sync += [
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qpll.reset.eq(self.qpll_reset.re),
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qpll.reset.eq(self.qpll_reset.re),
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@ -37,13 +28,10 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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]
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]
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for i, pad in enumerate(pads):
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for i in range(nconn):
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rx = Receiver(qpll, pad, sys_clk_freq, "single", "single", debug_sma, pmod_pads)
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if i != 0:
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self.rx_phys.append(rx)
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break
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setattr(self.submodules, "rx"+str(i), rx)
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gtx = GTX(self.qpll, pads[i], sys_clk_freq, tx_mode="single", rx_mode="single")
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self.gtxs.append(gtx)
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setattr(self.submodules, "gtx"+str(i), gtx)
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# TODO: add extension gtx connections
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# TODO: add extension gtx connections
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# TODO: add connection interface
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# TODO: add connection interface
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@ -52,126 +40,39 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# checkout channel interfaces & drtio_gtx
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# checkout channel interfaces & drtio_gtx
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# GTPTXPhaseAlignement for inspiration
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# GTPTXPhaseAlignement for inspiration
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# Connect all GTX connections' DRP
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self.gtx_daddr = CSRStorage(9)
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class Receiver(Module):
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self.gtx_dread = CSR()
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def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads):
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self.gtx_din_stb = CSR()
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self.submodules.gtx = gtx = GTX(qpll, pad, sys_clk_freq, tx_mode="single", rx_mode="single")
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self.gtx_din = CSRStorage(16)
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self.gtx_dout = CSRStatus(16)
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# DEBUG: remove cdc rx fifo
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self.gtx_dready = CSR()
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for gtx in self.gtxs:
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self.sync += [
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gtx.txenable.eq(self.txenable.storage[0]),
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gtx.tx_restart.eq(self.tx_restart.re),
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gtx.rx_restart.eq(self.rx_restart.re),
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gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
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gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
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]
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self.comb += gtx.dclk.eq(ClockSignal("sys"))
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self.sync += [
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gtx.den.eq(0),
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gtx.dwen.eq(0),
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If(self.gtx_dread.re,
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gtx.den.eq(1),
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gtx.daddr.eq(self.gtx_daddr.storage),
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).Elif(self.gtx_din_stb.re,
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gtx.den.eq(1),
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gtx.dwen.eq(1),
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gtx.daddr.eq(self.gtx_daddr.storage),
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gtx.din.eq(self.gtx_din.storage),
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),
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]
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# TODO: deal with 4 GTX instance of outpus
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for n, gtx in enumerate(self.gtxs):
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self.sync += [
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self.rx_ready.status[n].eq(gtx.rx_ready),
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If(gtx.dready,
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self.gtx_dready.w.eq(1),
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self.gtx_dout.status.eq(gtx.dout),
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),
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If(self.gtx_dready.re,
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self.gtx_dready.w.eq(0),
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),
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]
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self.sources = []
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for n, gtx in enumerate(self.gtxs):
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# DEBUG: remove cdc fifo
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# gtx rx -> fifo out -> cdc out
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# gtx rx -> fifo out -> cdc out
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fifo_out = stream.AsyncFIFO(downconn_layout, 512)
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rx_fifo = stream.AsyncFIFO(word_layout, 512)
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self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(fifo_out)
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self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(rx_fifo)
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self.sources.append(fifo_out)
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self.source = rx_fifo.source
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for i in range(4):
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for i in range(4):
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self.sync.cxp_gtx_rx += [
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self.sync.cxp_gtx_rx += [
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fifo_out.sink.stb.eq(0),
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rx_fifo.sink.stb.eq(0),
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# don't store idle word in fifo
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# don't store idle word in fifo
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If((gtx.rx_ready & fifo_out.sink.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1))),
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If((gtx.rx_ready & rx_fifo.sink.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1))),
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fifo_out.sink.stb.eq(1),
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rx_fifo.sink.stb.eq(1),
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fifo_out.sink.data[i*8:(i*8)+8].eq(gtx.decoders[i].d),
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rx_fifo.sink.data[i*8:(i*8)+8].eq(gtx.decoders[i].d),
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fifo_out.sink.k[i].eq(gtx.decoders[i].k),
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rx_fifo.sink.k[i].eq(gtx.decoders[i].k),
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),
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),
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]
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]
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# DEBUG: tx fifos for loopback
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# DEBUG: tx of gtx is not used in CXP
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# DEBUG: txusrclk PLL DRG
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self.txpll_reset = CSRStorage()
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self.pll_daddr = CSRStorage(7)
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self.pll_dclk = CSRStorage()
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self.pll_den = CSRStorage()
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self.pll_din = CSRStorage(16)
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self.pll_dwen = CSRStorage()
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self.txpll_locked = CSRStatus()
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self.pll_dout = CSRStatus(16)
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self.pll_dready = CSRStatus()
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self.txinit_phaligndone = CSRStatus()
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self.rxinit_phaligndone = CSRStatus()
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self.tx_stb = CSRStorage()
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self.sinks = []
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for n, gtx in enumerate(self.gtxs):
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self.comb += [
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gtx.txpll_reset.eq(self.txpll_reset.storage),
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gtx.pll_daddr.eq(self.pll_daddr.storage),
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gtx.pll_dclk.eq(self.pll_dclk.storage),
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gtx.pll_den.eq(self.pll_den.storage),
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gtx.pll_din.eq(self.pll_din.storage),
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gtx.pll_dwen.eq(self.pll_dwen.storage),
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self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone), self.txpll_locked.status.eq(gtx.txpll_locked),
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self.pll_dout.status.eq(gtx.pll_dout),
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self.pll_dready.status.eq(gtx.pll_dready),
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]
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# DEBUG:loopback
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self.loopback_mode = CSRStorage(3)
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self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage)
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# DEBUG: datain
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# fw -> fifo (sys) -> cdc fifo -> gtx tx
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# fw -> fifo (sys) -> cdc fifo -> gtx tx
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fifo_in = stream.AsyncFIFO(downconn_layout, 512)
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tx_fifo = stream.AsyncFIFO(word_layout, 512)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(tx_fifo)
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self.sinks.append(fifo_in)
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self.sink = tx_fifo.sink
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# TODO: why there this send an extra 0xFB word
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self.tx_stb_sys = Signal()
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txstb = Signal()
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txstb = Signal()
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self.specials += MultiReg(self.tx_stb.storage, txstb, odomain="cxp_gtx_tx")
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self.specials += MultiReg(self.tx_stb_sys, txstb, odomain="cxp_gtx_tx")
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word_count = Signal(max=100)
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word_count = Signal(max=100)
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@ -180,13 +81,13 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# out fifo[97] IDLE IDLE fifo[99]
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# out fifo[97] IDLE IDLE fifo[99]
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# ack 1 0 0 1
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# ack 1 0 0 1
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self.sync.cxp_gtx_tx += [
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self.sync.cxp_gtx_tx += [
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fifo_in.source.ack.eq(0),
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tx_fifo.source.ack.eq(0),
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If(word_count == 99,
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If(word_count == 99,
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word_count.eq(word_count.reset),
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word_count.eq(word_count.reset),
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).Else(
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).Else(
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If(fifo_in.source.stb & txstb,
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If(tx_fifo.source.stb & txstb,
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If(word_count != 98, fifo_in.source.ack.eq(1)),
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If(word_count != 98, tx_fifo.source.ack.eq(1)),
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word_count.eq(word_count + 1),
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word_count.eq(word_count + 1),
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)
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)
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)
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)
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@ -194,15 +95,15 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# NOTE: prevent the first word send twice due to stream stb delay
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# NOTE: prevent the first word send twice due to stream stb delay
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self.comb += [
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self.comb += [
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If((fifo_in.source.stb & fifo_in.source.ack & (word_count != 99)),
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If((tx_fifo.source.stb & tx_fifo.source.ack & (word_count != 99)),
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gtx.encoder.d[0].eq(fifo_in.source.data[:8]),
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gtx.encoder.d[0].eq(tx_fifo.source.data[:8]),
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gtx.encoder.d[1].eq(fifo_in.source.data[8:16]),
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gtx.encoder.d[1].eq(tx_fifo.source.data[8:16]),
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gtx.encoder.d[2].eq(fifo_in.source.data[16:24]),
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gtx.encoder.d[2].eq(tx_fifo.source.data[16:24]),
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gtx.encoder.d[3].eq(fifo_in.source.data[24:]),
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gtx.encoder.d[3].eq(tx_fifo.source.data[24:]),
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gtx.encoder.k[0].eq(fifo_in.source.k[0]),
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gtx.encoder.k[0].eq(tx_fifo.source.k[0]),
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gtx.encoder.k[1].eq(fifo_in.source.k[1]),
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gtx.encoder.k[1].eq(tx_fifo.source.k[1]),
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gtx.encoder.k[2].eq(fifo_in.source.k[2]),
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gtx.encoder.k[2].eq(tx_fifo.source.k[2]),
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gtx.encoder.k[3].eq(fifo_in.source.k[3]),
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gtx.encoder.k[3].eq(tx_fifo.source.k[3]),
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).Else(
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).Else(
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# NOTE: IDLE WORD
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# NOTE: IDLE WORD
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gtx.encoder.d[0].eq(0xBC),
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gtx.encoder.d[0].eq(0xBC),
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@ -216,27 +117,6 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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)
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)
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]
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]
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# DEBUG: IO SMA & PMOD
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if n == 0:
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self.specials += [
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# Instance("OBUF", i_I=gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
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# Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# # pmod 0-7 pin
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# Instance("OBUF", i_I=txstb, o_O=pmod_pads[0]),
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# Instance("OBUF", i_I=fifo_in.source.stb, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=gtx.comma_checker.has_error, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=gtx.comma_checker.ready_sys, o_O=pmod_pads[7]),
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# Instance("OBUF", i_I=gtx.dclk, o_O=pmod_pads[0]),
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# Instance("OBUF", i_I=gtx.den, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=gtx.dwen, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=gtx.dready, o_O=pmod_pads[3]),
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]
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class QPLL(Module, AutoCSR):
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class QPLL(Module, AutoCSR):
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def __init__(self, refclk, sys_clk_freq):
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def __init__(self, refclk, sys_clk_freq):
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