forked from M-Labs/artiq-zynq
cxp: add clk_reset & tx_busy csr
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c06d9f8485
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535b79cfd4
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@ -27,19 +27,24 @@ class UpConn_Packets(Module, AutoCSR):
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self.tag_counts = Signal(max=0xFF)
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self.use_tag = Signal()
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self.clk_reset = CSRStorage(reset=1)
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self.bitrate2x_enable = CSRStorage()
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self.tx_enable = CSRStorage()
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self.tx_busy = CSRStatus()
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self.encoded_data = CSRStatus(10)
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# # #
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self.submodules.upconn = upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout(), fifos_depth)
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self.comb += [
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self.sync += [
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upconn.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
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upconn.tx_enable.eq(self.tx_enable.storage),
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upconn.clk_reset.eq(self.clk_reset.re),
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self.tx_busy.status.eq(upconn.tx_busy),
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]
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self.sync += [
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self.encoded_data.status.eq(upconn.scheduler.encoder.output),
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]
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