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cxp downconn fw: remove data[4:8]

This commit is contained in:
morgan 2024-07-26 17:01:54 +08:00
parent 1a210a010a
commit 52f77a6331
1 changed files with 9 additions and 13 deletions
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22
src/libboard_artiq/src/cxp_downconn.rs
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@ -17,7 +17,7 @@ pub fn main(timer: &mut GlobalTimer) {
// send K28_5 for CDR to align // send K28_5 for CDR to align
const K28_5: u8 = 0xBC; const K28_5: u8 = 0xBC;
const K28_1: u8 = 0x3C; const K28_1: u8 = 0x3C;
const D21_5: u8 = 21 << 5 | 5; const D21_5: u8 = 21 | 5 << 5;
// brute force aligner only align K28_5 on rxdata[:10] // brute force aligner only align K28_5 on rxdata[:10]
// don't send too much K28_5 in case phase is locked on the wrong stuff // don't send too much K28_5 in case phase is locked on the wrong stuff
// seems like I need at least 2 K28_5 to work // seems like I need at least 2 K28_5 to work
@ -28,31 +28,23 @@ pub fn main(timer: &mut GlobalTimer) {
// 156.25MHz OK // 156.25MHz OK
// 250MHz // 250MHz
// 312.5MHz // 312.5MHz
const LEN: usize = 8; const LEN: usize = 4;
const DATA: [[u8; LEN]; 2] = [ const DATA: [[u8; LEN]; 2] = [
// [K28_5, K28_5, K28_5, K28_1, K28_5, K28_5, K28_5, K28_5], // [K28_5, K28_5, K28_5, K28_1, K28_5, K28_5, K28_5, K28_5],
// [1, 1, 1, 1, 1, 1, 1, 1], // [1, 1, 1, 1, 1, 1, 1, 1],
[K28_5, K28_1, K28_1, D21_5, K28_5, K28_1, K28_1, D21_5], [K28_5, K28_1, K28_1, D21_5],
[1, 1, 1, 0, 1, 1, 1, 0], [1, 1, 1, 0],
]; ];
csr::cxp::data_0_write(DATA[0][0]); csr::cxp::data_0_write(DATA[0][0]);
csr::cxp::data_1_write(DATA[0][1]); csr::cxp::data_1_write(DATA[0][1]);
csr::cxp::data_2_write(DATA[0][2]); csr::cxp::data_2_write(DATA[0][2]);
csr::cxp::data_3_write(DATA[0][3]); csr::cxp::data_3_write(DATA[0][3]);
csr::cxp::data_4_write(DATA[0][4]);
csr::cxp::data_5_write(DATA[0][5]);
csr::cxp::data_6_write(DATA[0][6]);
csr::cxp::data_7_write(DATA[0][7]);
csr::cxp::control_bit_0_write(DATA[1][0]); csr::cxp::control_bit_0_write(DATA[1][0]);
csr::cxp::control_bit_1_write(DATA[1][1]); csr::cxp::control_bit_1_write(DATA[1][1]);
csr::cxp::control_bit_2_write(DATA[1][2]); csr::cxp::control_bit_2_write(DATA[1][2]);
csr::cxp::control_bit_3_write(DATA[1][3]); csr::cxp::control_bit_3_write(DATA[1][3]);
csr::cxp::control_bit_4_write(DATA[1][4]);
csr::cxp::control_bit_5_write(DATA[1][5]);
csr::cxp::control_bit_6_write(DATA[1][6]);
csr::cxp::control_bit_7_write(DATA[1][7]);
// enable cxp gtx clock domains // enable cxp gtx clock domains
csr::cxp::tx_start_init_write(1); csr::cxp::tx_start_init_write(1);
@ -105,7 +97,11 @@ pub fn main(timer: &mut GlobalTimer) {
} }
pub fn change_linerate() { pub fn change_linerate() {
// TODO: switch CPLL/QPLL divider for RXUSRCLK // TODO: switch QPLL divider for RXUSRCLK
// TODO: switch TX/RXDIV via TX/RXRATE
// no need for DRP for this
// TODO: switch pll for TXUSRCLK = freq(linerate)/20 // TODO: switch pll for TXUSRCLK = freq(linerate)/20
// TODO: reset tx&rx for phase alignment // TODO: reset tx&rx for phase alignment
} }