From 526ec3fc1361eab34e7bec60b9da118bd723a1cb Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Tue, 23 Jul 2024 16:40:17 +0800
Subject: [PATCH] cxp upconn firmware: packet testing

cxp upconn FW: fix multilane tx issue

upconn fw: rename to cxp mem
---
 src/libboard_artiq/src/cxp_upconn.rs | 91 ++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 src/libboard_artiq/src/cxp_upconn.rs

diff --git a/src/libboard_artiq/src/cxp_upconn.rs b/src/libboard_artiq/src/cxp_upconn.rs
new file mode 100644
index 0000000..1b3dc4e
--- /dev/null
+++ b/src/libboard_artiq/src/cxp_upconn.rs
@@ -0,0 +1,91 @@
+use core::slice;
+
+use embedded_hal::blocking::delay::DelayUs;
+use io::Cursor;
+use libboard_zynq::{println, timer::GlobalTimer};
+
+use crate::{cxp_proto,
+            mem::mem::CXP_MEM,
+            pl::csr::{self, CXP}};
+const BUF_LEN: usize = 0x800;
+
+pub fn tx_test(channel: u8, timer: &mut GlobalTimer) {
+    const LEN: usize = 4 * 100;
+    let mut pak_arr: [u8; LEN] = [0; LEN];
+
+    let channel = channel as usize;
+    unsafe {
+        (CXP[channel].upconn_trig_delay_write)(0x86);
+        (CXP[channel].upconn_linktrigger_write)(0x00);
+
+        // DEBUG: prepare the packet before tx enable to avoid overhead
+        preload_tx_packet(
+            channel as u8,
+            &cxp_proto::UpConnPacket::CtrlRead {
+                tag: None,
+                addr: 0,
+                length: 4,
+            },
+        );
+
+        csr::cxp_phys::upconn_tx_enable_write(1);
+        timer.delay_us(1);
+
+        // DEBUG: send ctrl packet or test
+        (CXP[channel].upconn_bootstrap_tx_write)(1);
+        (CXP[channel].upconn_bootstrap_tx_testseq_write)(1);
+
+        // DEBUG: Trigger packet (NOTE: disconnected in Gateware)
+        // (CXP[channel].upconn_trig_stb_write)(1); // send trig
+
+        // DEBUG: Trigger ACK packet
+        // (CXP[channel].upconn_ack_write)(1);
+
+        timer.delay_us(2000);
+        csr::cxp_phys::upconn_tx_enable_write(0);
+
+        // Collect data
+        let mut i: usize = 0;
+        match channel {
+            0 => {
+                while csr::cxp_phys::upconn_tx0_debug_buf_dout_valid_read() == 1 {
+                    pak_arr[i] = csr::cxp_phys::upconn_tx0_debug_buf_dout_pak_read();
+                    csr::cxp_phys::upconn_tx0_debug_buf_inc_write(1);
+                    i += 1;
+                    if i == LEN {
+                        break;
+                    }
+                }
+            }
+            1 => {
+                while csr::cxp_phys::upconn_tx1_debug_buf_dout_valid_read() == 1 {
+                    pak_arr[i] = csr::cxp_phys::upconn_tx1_debug_buf_dout_pak_read();
+                    csr::cxp_phys::upconn_tx1_debug_buf_inc_write(1);
+                    i += 1;
+                    if i == LEN {
+                        break;
+                    }
+                }
+            }
+            _ => {}
+        }
+
+        cxp_proto::print_packet(&pak_arr);
+    }
+}
+
+fn preload_tx_packet(channel: u8, packet: &cxp_proto::UpConnPacket) {
+    let channel = channel as usize;
+    unsafe {
+        while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {}
+        let ptr = CXP_MEM[channel].base as *mut u32;
+        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
+
+        packet.write_to(&mut writer).expect("unstable to write to tx mem");
+        // DEBUG:
+        println!("TX MEM after writing");
+        cxp_proto::print_packet(&writer.get_ref()[0..40]);
+
+        (CXP[channel].upconn_bootstrap_tx_word_len_write)(writer.position() as u16 / 4);
+    }
+}