forked from M-Labs/artiq-zynq
support absence of gateware RTIO clock selection mux
This commit is contained in:
parent
8815f76114
commit
506c741238
|
@ -83,6 +83,7 @@ class ZC706(SoCCore):
|
||||||
|
|
||||||
self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
|
self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
|
||||||
self.csr_devices.append("rtio_crg")
|
self.csr_devices.append("rtio_crg")
|
||||||
|
self.rustc_cfg["has_rtio_crg_clock_sel"] = None
|
||||||
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
|
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
|
||||||
self.platform.add_false_path_constraints(
|
self.platform.add_false_path_constraints(
|
||||||
self.ps7.cd_sys.clk,
|
self.ps7.cd_sys.clk,
|
||||||
|
|
|
@ -108,6 +108,7 @@ fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
|
||||||
loop {
|
loop {
|
||||||
unsafe {
|
unsafe {
|
||||||
pl::csr::rtio_crg::pll_reset_write(1);
|
pl::csr::rtio_crg::pll_reset_write(1);
|
||||||
|
#[cfg(has_rtio_crg_clock_sel)]
|
||||||
pl::csr::rtio_crg::clock_sel_write(clock_sel);
|
pl::csr::rtio_crg::clock_sel_write(clock_sel);
|
||||||
pl::csr::rtio_crg::pll_reset_write(0);
|
pl::csr::rtio_crg::pll_reset_write(0);
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue