forked from M-Labs/artiq-zynq
rtio_clocking: fix wrong descriptions
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@ -136,7 +136,7 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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}
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}
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},
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},
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 10,
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n1_hs : 10,
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nc1_ls : 4,
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nc1_ls : 4,
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@ -149,7 +149,7 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
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}
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}
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},
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},
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RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
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info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
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info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
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si5324::FrequencySettings {
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si5324::FrequencySettings {
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n1_hs : 5,
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n1_hs : 5,
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nc1_ls : 8,
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nc1_ls : 8,
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