forked from M-Labs/artiq-zynq
cxp pipeline: remove crc inserter & pak_type
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f49f3dbb55
commit
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@ -243,22 +243,16 @@ class Trigger_ACK(Module):
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class TX_Command_Packet(Module, AutoCSR):
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class TX_Command_Packet(Module, AutoCSR):
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def __init__(self, layout):
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def __init__(self, layout):
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self.packet_type = CSRStorage(8)
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self.din_len = CSRStorage(6)
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self.din_len = CSRStorage(6)
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self.din_data = CSR(8)
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self.din_data = CSR(8)
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self.din_k = CSRStorage()
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self.din_ready = CSRStatus()
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self.din_ready = CSRStatus()
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# # #
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# # #
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# a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available
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# a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available
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# otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source
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# otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source
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self.submodules.buf_in = buf_in = stream.SyncFIFO(layout, 2)
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self.submodules.buf_in = buf_in = stream.SyncFIFO(layout, 2)
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self.submodules.crc_inserter = crc_inserters = CXPCRC32Inserter(layout)
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self.submodules.pak_type = pak_type = Code_Inserter(layout)
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
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len = Signal(6, reset=1)
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len = Signal(6, reset=1)
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@ -275,18 +269,9 @@ class TX_Command_Packet(Module, AutoCSR):
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),
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),
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buf_in.sink.stb.eq(1),
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buf_in.sink.stb.eq(1),
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buf_in.sink.data.eq(self.din_data.r),
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buf_in.sink.data.eq(self.din_data.r),
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buf_in.sink.k.eq(self.din_k.storage),
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buf_in.sink.k.eq(0),
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),
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),
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]
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]
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self.comb += [
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self.comb += buf_in.source.connect(pak_wrp.sink),
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pak_type.data.eq(self.packet_type.storage),
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self.source = pak_wrp.source
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pak_type.k.eq(0),
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]
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tx_pipeline = [ buf_in, crc_inserters, pak_type, pak_wrp]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.source = tx_pipeline[-1].source
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