diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index 8dc691c..a9d6213 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -243,22 +243,16 @@ class Trigger_ACK(Module):
 
 class TX_Command_Packet(Module, AutoCSR):
     def __init__(self, layout):
-        self.packet_type = CSRStorage(8)
-
         self.din_len = CSRStorage(6)
         self.din_data = CSR(8)
-        self.din_k = CSRStorage()
         self.din_ready = CSRStatus()
 
         # # #
 
-
         # a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available
         # otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source
         self.submodules.buf_in = buf_in = stream.SyncFIFO(layout, 2)
 
-        self.submodules.crc_inserter = crc_inserters = CXPCRC32Inserter(layout)
-        self.submodules.pak_type = pak_type = Code_Inserter(layout)
         self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(layout)
         
         len = Signal(6, reset=1)
@@ -275,18 +269,9 @@ class TX_Command_Packet(Module, AutoCSR):
                 ),
                 buf_in.sink.stb.eq(1),
                 buf_in.sink.data.eq(self.din_data.r),
-                buf_in.sink.k.eq(self.din_k.storage),
+                buf_in.sink.k.eq(0),
             ),
         ]
 
-        self.comb += [
-            pak_type.data.eq(self.packet_type.storage),
-            pak_type.k.eq(0),
-        ]
-        
-        tx_pipeline = [ buf_in, crc_inserters, pak_type, pak_wrp]
-
-        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
-            self.comb += s.source.connect(d.sink)
-
-        self.source = tx_pipeline[-1].source
+        self.comb += buf_in.source.connect(pak_wrp.sink),
+        self.source = pak_wrp.source