morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp upconn: use singlencoder & fix disparity bug

This commit is contained in:
morgan 2024-06-18 14:40:58 +08:00
parent 7c60fb5776
commit 4de58e0d52
1 changed files with 20 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
src/gateware/cxp_upconn.py
View File

@ -2,7 +2,7 @@ from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.genlib.cdc import MultiReg
from misoc.cores.code_8b10b import Encoder, Decoder
from misoc.cores.code_8b10b import SingleEncoder, Decoder
from misoc.interconnect.csr import *
from misoc.interconnect import stream
@ -48,8 +48,6 @@ class CXP_UpConn(Module, AutoCSR):
AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
]
self.submodules.encoder = ClockDomainsRenamer("cxp_upconn")(Encoder(1))
self.stb = CSRStorage()
self.data = CSRStorage(8)
self.k_symbol = CSRStorage()
@ -62,24 +60,27 @@ class CXP_UpConn(Module, AutoCSR):
tx_reg = Signal(tx_width)
busy = Signal()
fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="IDLE"))
self.submodules += fsm
self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="IDLE"))
self.submodules.encoder = SingleEncoder(True)
fsm.act("IDLE",
self.fsm.act("IDLE",
NextValue(o, 0),
If(self.stb.storage,
NextValue(bits, 0),
NextValue(tx_reg, self.encoder.output[0]),
NextValue(self.tx_reg.status, self.encoder.output[0]),
NextValue(tx_reg, self.encoder.output),
NextValue(self.tx_reg.status, self.encoder.output),
NextValue(self.encoder.disp_in, self.encoder.disp_out),
NextState("WRITE")
)
)
fsm.act("WRITE",
self.fsm.act("WRITE",
If(bits == tx_width - 1,
If(self.stb.storage,
NextValue(bits, 0),
NextValue(o, self.encoder.output[0][0]),
NextValue(tx_reg, Cat(self.encoder.output[0][1:], 0)),
NextValue(tx_reg, Cat(self.encoder.output[1:], 0)),
NextValue(self.tx_reg.status, self.encoder.output),
NextValue(self.encoder.disp_in, self.encoder.disp_out),
).Else(
NextState("IDLE"),
)
@ -90,12 +91,16 @@ class CXP_UpConn(Module, AutoCSR):
),
)
self.sync.cxp_upconn +=[
self.encoder.d[0].eq(self.data.storage),
self.encoder.k[0].eq(self.k_symbol.storage),
self.encoded.status.eq(self.encoder.output[0]),
self.comb += [
self.encoder.d.eq(self.data.storage),
self.encoder.k.eq(self.k_symbol.storage),
]
self.comb += busy.eq(~fsm.ongoing("IDLE"))
self.sync.cxp_upconn +=[
self.encoded.status.eq(self.encoder.output),
]
self.comb += busy.eq(~self.fsm.ongoing("IDLE"))
# DEBUG: remove pads
self.specials += [
Instance("OBUF", i_I=o, o_O=pads.p_tx),