cxp pipeline: add code port for code inserter

src/gateware/cxp_pipeline.py

@@ -16,10 +16,13 @@ class Code_Inserter(Module):
         Preamble, SFD, and packet octets.
     """
 
-    def __init__(self, data, k, cxp_phy_layout, insert_infront=True, counts=4):
+    def __init__(self, cxp_phy_layout, insert_infront=True, counts=4):
         self.sink = sink = stream.Endpoint(cxp_phy_layout)
         self.source = source = stream.Endpoint(cxp_phy_layout)
 
+        self.data = Signal.like(sink.data)
+        self.k = Signal.like(sink.k)
+
         # # #
 
         cnt = Signal(max=counts)
@@ -48,8 +51,8 @@ class Code_Inserter(Module):
         if insert_infront:
             fsm.act("INSERT",
                 source.stb.eq(1), # = writing data now
-                source.data.eq(data),
+                source.data.eq(self.data),
-                source.k.eq(k),
+                source.k.eq(self.k),
                 If(cnt == counts - 1,
                     If(source.ack, NextState("COPY"))
                 ).Else(
@@ -60,14 +63,8 @@ class Code_Inserter(Module):
             pass
 
         
-        # NOTE: why??
-        self.comb += [
-            source.data.eq(sink.data),
-            source.k.eq(sink.k),
-        ]
-        
         fsm.act("COPY",
-            sink.connect(source, omit={"data", "k"}),
+            sink.connect(source),
 
             # eop = end of packet?
             If(sink.stb & sink.eop & source.ack,
@@ -76,6 +73,20 @@ class Code_Inserter(Module):
             
         )
 
+def K(x, y):
+    return ((y << 5) | x)
+
+def D(x, y):
+    return ((y << 5) | x)
+
+class Packet_Start_Inserter(Code_Inserter):
+    def __init__(self, layout):
+        Code_Inserter.__init__(self, layout)
+        self.comb += [
+            self.data.eq(K(27, 7)),
+            self.k.eq(1),
+        ]
+
 @ResetInserter()
 @CEInserter()
 class CXPCRC32(Module):