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cxp GW: remove unused debug port

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morgan 2025-01-16 12:15:20 +08:00
parent 30e345ef67
commit 4d1d04c71b
1 changed files with 8 additions and 30 deletions
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38
src/gateware/cxp.py
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@ -28,9 +28,9 @@ class CXP_PHYS(Module, AutoCSR):
class CXP_Core(Module, AutoCSR): class CXP_Core(Module, AutoCSR):
def __init__(self, phy, debug_sma, pmod_pads): def __init__(self, phy):
self.submodules.tx = TX_Pipeline(phy.tx, debug_sma, pmod_pads) self.submodules.tx = TX_Pipeline(phy.tx)
self.submodules.rx = RX_Pipeline(phy.rx, debug_sma, pmod_pads) self.submodules.rx = RX_Pipeline(phy.rx)
def get_tx_port(self): def get_tx_port(self):
return self.tx.writer.mem.get_port(write_capable=True) return self.tx.writer.mem.get_port(write_capable=True)
@ -59,7 +59,7 @@ class CXP_Core(Module, AutoCSR):
class CXP_Master(CXP_Core): class CXP_Master(CXP_Core):
def __init__(self, phy, debug_sma, pmod_pads): def __init__(self, phy, debug_sma, pmod_pads):
CXP_Core.__init__(self, phy, debug_sma, pmod_pads) CXP_Core.__init__(self, phy)
nbit_trigdelay = 8 nbit_trigdelay = 8
nbit_linktrig = 1 nbit_linktrig = 1
@ -81,12 +81,12 @@ class CXP_Master(CXP_Core):
# self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx), # self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx),
class CXP_Extension(CXP_Core): class CXP_Extension(CXP_Core):
def __init__(self, phy, debug_sma, pmod_pads): def __init__(self, phy):
CXP_Core.__init__(self, phy, debug_sma, pmod_pads) CXP_Core.__init__(self, phy)
class RX_Pipeline(Module, AutoCSR): class RX_Pipeline(Module, AutoCSR):
def __init__(self, phy, debug_sma, pmod_pads): def __init__(self, phy):
self.ready = CSRStatus() self.ready = CSRStatus()
# # # # # #
@ -221,13 +221,6 @@ class RX_Pipeline(Module, AutoCSR):
) )
] ]
# DEBUG:
# # add buffer to improve timing & reduce tight setup/hold time
# self.submodules.buffer_cdc_fifo = buffer_cdc_fifo = cdr(Buffer(word_layout_dchar))
# cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 512)
# self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
# self.submodules.debug_out = debug_out = RX_Debug_Buffer(word_layout_dchar)
# Drop the K29.7 and mark the EOP for arbiter and crc cheker # Drop the K29.7 and mark the EOP for arbiter and crc cheker
self.submodules.eop_marker = eop_marker = cdr(EOP_Marker()) self.submodules.eop_marker = eop_marker = cdr(EOP_Marker())
@ -247,7 +240,7 @@ class RX_Pipeline(Module, AutoCSR):
class TX_Pipeline(Module, AutoCSR): class TX_Pipeline(Module, AutoCSR):
def __init__(self, phy, debug_sma, pmod_pads): def __init__(self, phy):
# Transmission Pipeline # Transmission Pipeline
# #
# 32 32 8 # 32 32 8
@ -269,25 +262,10 @@ class TX_Pipeline(Module, AutoCSR):
# 0: Trigger packet # 0: Trigger packet
self.submodules.trig = trig = Trigger_Inserter() self.submodules.trig = trig = Trigger_Inserter()
# # DEBUG: INPUT
self.trig_stb = CSR()
self.trig_delay = CSRStorage(8)
self.linktrigger = CSRStorage()
# self.sync += [
# trig.stb.eq(self.trig_stb.re),
# trig.delay.eq(self.trig_delay.storage),
# trig.linktrig_mode.eq(self.linktrigger.storage),
# ]
# 1: IO acknowledgment for trigger packet # 1: IO acknowledgment for trigger packet
self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter() self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
# DEBUG: INPUT
self.ack = CSR()
self.sync += trig_ack.stb.eq(self.ack.re),
# 2: All other packets (data & test packet) # 2: All other packets (data & test packet)
# Control is not timing dependent, all the data packets are handled in firmware # Control is not timing dependent, all the data packets are handled in firmware