diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index 72f0305..1932d4e 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -184,10 +184,16 @@ class DownConn_Interface(Module, AutoCSR):
         self.submodules += test_reset_ps
         self.sync += test_reset_ps.i.eq(self.bootstrap_test_counts_reset.re),
 
-        self.sync.cxp_gtx_rx += bootstrap.test_cnt_reset.eq(test_reset_ps.o),
+        test_err_cnt_r = Signal.like(bootstrap.test_err_cnt)
+        test_pak_cnt_r = Signal.like(bootstrap.test_pak_cnt)
+        self.sync.cxp_gtx_rx += [ 
+            bootstrap.test_cnt_reset.eq(test_reset_ps.o),
+            test_err_cnt_r.eq(bootstrap.test_err_cnt),
+            test_pak_cnt_r.eq(bootstrap.test_pak_cnt),
+        ]
         self.specials += [
-            MultiReg(bootstrap.test_err_cnt, self.bootstrap_test_error_counter.status),
-            MultiReg(bootstrap.test_pak_cnt, self.bootstrap_test_packet_counter.status),
+            MultiReg(test_err_cnt_r, self.bootstrap_test_error_counter.status),
+            MultiReg(test_pak_cnt_r, self.bootstrap_test_packet_counter.status),
         ]
 
         # Cicular buffer interface
@@ -286,9 +292,9 @@ class UpConn_Interface(Module, AutoCSR):
         for s, d in zip(tx_pipeline, tx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
 
-class CXP_Frame_Buffer(Module, AutoCSR):
+class CXP_Frame_Pipeline(Module, AutoCSR):
     # optimal stream packet size is 2 KiB - Section 9.5.2 (CXP-001-2021)
-    def __init__(self, downconns, pmod_pads, packet_size=16384, n_buffer=2):
+    def __init__(self, downconns, pmod_pads, packet_size=16384, n_buffer=1):
         n_downconn = len(downconns)
         
         framebuffers = []
@@ -302,33 +308,41 @@ class CXP_Frame_Buffer(Module, AutoCSR):
                 arr_csr.append(csr)
                 setattr(self, name, csr)
 
-            crc_checker = cdr(CXPCRC32_Checker())
-
-            # TODO: handle full buffer gracefully
-
-            # TODO: investigate why there is a heartbeat message in the middle of the frame with k27.7 code too???
-            # NOTE: sometimes there are 0xFBFBFBFB K=0b1111
-            # perhaps the buffer is full overflowing and doing strange stuff             
-
-            # it should be mem block not "cycle buffer"
-            # self.submodules.dropper = dropper = cdr(DChar_Dropper())
-            buffer_cdc_fifo = cdr(Buffer(word_layout_dchar)) # to improve timing
-            cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 2**log2_int(packet_size//word_dw))
-            self.submodules += crc_checker, buffer_cdc_fifo
-            self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
-
-            pipeline = [crc_checker, buffer_cdc_fifo, cdc_fifo]
-            for s, d in zip(pipeline, pipeline[1:]):
-                self.comb += s.source.connect(d.sink)
-            framebuffers.append(pipeline[0])
+            roi_pipeline = ROI_Pipeline()
+            self.submodules += roi_pipeline
+            framebuffers.append(roi_pipeline.pipeline[0])
 
             # DEBUG:
-            if i == 0:
-                self.submodules.debug_out = debug_out = RX_Debug_Buffer(word_layout_dchar, 2**log2_int(packet_size//word_dw))
-                self.comb += pipeline[-1].source.connect(debug_out.sink)
-            else:
-                # remove any backpressure 
-                self.comb += pipeline[-1].source.ack.eq(1)
+            # self.comb += roi_pipeline.pipeline[-1].source.ack.eq(1)
+
+
+            # crc_checker = cdr(CXPCRC32_Checker())
+
+            # # TODO: handle full buffer gracefully
+            # # TODO: investigate why there is a heartbeat message in the middle of the frame with k27.7 code too???
+            # # NOTE: sometimes there are 0xFBFBFBFB K=0b1111
+            # # perhaps the buffer is full overflowing and doing strange stuff             
+
+            # # it should be mem block not "cycle buffer"
+            # # self.submodules.dropper = dropper = cdr(DChar_Dropper())
+            # buffer_cdc_fifo = cdr(Buffer(word_layout_dchar)) # to improve timing
+            # cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 2**log2_int(packet_size//word_dw))
+            # self.submodules += crc_checker, buffer_cdc_fifo
+            # self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
+
+            # pipeline = [crc_checker, buffer_cdc_fifo, cdc_fifo]
+            # for s, d in zip(pipeline, pipeline[1:]):
+            #     self.comb += s.source.connect(d.sink)
+            # framebuffers.append(pipeline[0])
+            
+
+            # # DEBUG:
+            # if i == 0:
+            #     self.submodules.debug_out = debug_out = RX_Debug_Buffer(word_layout_dchar, 2**log2_int(packet_size//word_dw))
+            #     self.comb += pipeline[-1].source.connect(debug_out.sink)
+            # else:
+            #     # remove any backpressure 
+            #     self.comb += pipeline[-1].source.ack.eq(1)
 
 
         self.submodules.router = router = cdr(Frame_Packet_Router(downconns, framebuffers, packet_size, pmod_pads))