forked from M-Labs/artiq-zynq
cxp upconn fw: add trigger ack test
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@ -3,6 +3,37 @@ use libboard_zynq::{println, timer::GlobalTimer};
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use crate::pl::csr;
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pub fn trigger_ack_test(timer: &mut GlobalTimer) {
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const LEN: usize = 4 * 8;
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let mut pak_arr: [u8; LEN] = [0; LEN];
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unsafe {
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csr::cxp::txtrig_ack_write(1); // send IO ack
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let mut i: usize = 0;
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while csr::cxp::txtrig_dout_valid_read() == 1 {
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pak_arr[i] = csr::cxp::txtrig_dout_pak_read();
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// println!("received {:#04X}", pak_arr[i]);
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csr::cxp::txtrig_inc_write(1);
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i += 1;
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}
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println!("arr = [");
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for i in 0..(LEN / 4) {
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println!(
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"{:#03} {:#04X} {:#04X} {:#04X} {:#04X},",
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i + 1,
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pak_arr[i * 4],
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pak_arr[i * 4 + 1],
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pak_arr[i * 4 + 2],
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pak_arr[i * 4 + 3]
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)
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}
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println!("]");
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println!("============================================");
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}
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}
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pub fn pipeline_test(timer: &mut GlobalTimer) {
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let arr = [
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// 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08
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@ -24,10 +55,13 @@ pub fn pipeline_test(timer: &mut GlobalTimer) {
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csr::cxp::txcore_din_pak_write(*a);
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}
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// wait for pipelining
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timer.delay_us(1);
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let mut i: usize = 0;
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while csr::cxp::txcore_dout_valid_read() == 1 {
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pak_arr[i] = csr::cxp::txcore_dout_pak_read();
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println!("received {:#04X}", pak_arr[i]);
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// println!("received {:#04X}", pak_arr[i]);
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csr::cxp::txcore_inc_write(1);
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i += 1;
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}
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@ -35,14 +69,16 @@ pub fn pipeline_test(timer: &mut GlobalTimer) {
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println!("arr = [");
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for i in 0..(LEN / 4) {
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println!(
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" {:#04X} {:#04X} {:#04X} {:#04X},",
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"{:#03} {:#04X} {:#04X} {:#04X} {:#04X},",
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i + 1,
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pak_arr[i * 4],
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pak_arr[i * 4 + 1],
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pak_arr[i * 4 + 2],
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pak_arr[i * 4 + 3]
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)
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}
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println!("]")
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println!("]");
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println!("============================================");
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}
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}
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@ -95,6 +131,7 @@ pub fn tx_test(timer: &mut GlobalTimer) {
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)
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}
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println!("]");
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println!("============================================");
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timer.delay_us(2_000_000);
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}
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}
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