forked from M-Labs/artiq-zynq
cxp router: init
router:
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297
src/gateware/cxp_router.py
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297
src/gateware/cxp_router.py
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect.stream import Endpoint
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from cxp_pipeline import *
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# from src.gateware.cxp_pipeline import * # for sim only
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from types import SimpleNamespace
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from math import lcm
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from operator import or_, add
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word_layout_dchar_4x = [
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("data", 4*word_width),
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("k", 4*word_width//8),
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("dchar", 4*char_width),
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("dchar_k", 4*char_width//8),
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("valid", 4),
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]
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class Stream_Router(Module):
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"""
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Match the id and route stream packet to the correct downstream and strip the packet header
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"""
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def __init__(self, routing_ids=[0]):
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n_id = len(routing_ids)
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assert n_id > 0
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self.sources = [stream.Endpoint(word_layout_dchar) for _ in range(n_id)]
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self.sink = stream.Endpoint(word_layout_dchar)
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# # #
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stream_id = Signal(char_width)
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pak_tag = Signal(char_width)
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stream_pak_size = Signal(char_width * 2)
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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fsm.act(
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"WAIT_HEADER",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(stream_id, self.sink.dchar),
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NextState("GET_PAK_TAG"),
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),
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)
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fsm.act(
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"GET_PAK_TAG",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(pak_tag, self.sink.dchar),
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NextState("GET_PAK_SIZE_0"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_0",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(stream_pak_size[8:], self.sink.dchar),
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NextState("GET_PAK_SIZE_1"),
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),
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)
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routing_case = {"default": NextState("DISCARD")}
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for id in (routing_ids):
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routing_case[id] = [NextState(f"COPY_TO_BUFFER_{id}")]
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fsm.act(
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"GET_PAK_SIZE_1",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(stream_pak_size[:8], self.sink.dchar),
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Case(stream_id, routing_case),
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),
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)
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for key in routing_case:
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if key == "default":
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fsm.act(
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"DISCARD",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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NextValue(stream_pak_size, stream_pak_size - 1),
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If(stream_pak_size == 0,
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NextValue(stream_id, stream_id.reset),
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NextValue(pak_tag, pak_tag.reset),
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NextValue(stream_pak_size, stream_pak_size.reset),
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NextState("WAIT_HEADER"),
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)
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),
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)
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else:
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fsm.act(
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f"COPY_TO_BUFFER_{key}",
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self.sink.connect(self.sources[key]),
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# assume downstream is not blocked
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If(self.sink.stb,
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NextValue(stream_pak_size, stream_pak_size - 1),
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If(stream_pak_size == 0,
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NextValue(stream_id, stream_id.reset),
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NextValue(pak_tag, pak_tag.reset),
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NextValue(stream_pak_size, stream_pak_size.reset),
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NextState("WAIT_HEADER"),
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)
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),
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)
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class Stream_Packet_Gearbox(Module):
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"""
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1:4 gearbox
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"""
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def __init__(self):
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self.sink = Endpoint(word_layout_dchar)
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self.source = Endpoint(word_layout_dchar_4x)
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# # #
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# TODO: take into account of stbs
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sink_bits = len(self.sink.payload.raw_bits())
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source_bits = len(self.source.payload.raw_bits()) - 4 # 4 extra "valid" bits
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print(sink_bits, source_bits)
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assert source_bits/sink_bits == 4
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self.submodules.fsm = fsm = FSM(reset_state="0")
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ring_buf_size = lcm(sink_bits, source_bits)
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# ensure the shift register is at least twice the size of sink/source dw
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if (ring_buf_size//sink_bits) < 2:
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ring_buf_size = ring_buf_size * 2
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if (ring_buf_size//source_bits) < 2:
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ring_buf_size = ring_buf_size * 2
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ring_buffer_layout = []
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for name, width in word_layout_dchar:
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ring_buffer_layout.append(
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(name, width*ring_buf_size)
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)
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ring_buffer = Record(ring_buffer_layout)
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# Control interface
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reset_reg = Signal()
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we = Signal()
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re = Signal()
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level = Signal(max=ring_buf_size)
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w_cnt = Signal(max=ring_buf_size//sink_bits)
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r_cnt = Signal(max=ring_buf_size//source_bits)
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self.sync += [
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If(reset_reg,
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level.eq(level.reset),
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).Else(
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If(we & ~re, level.eq(level + sink_bits)),
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If(~we & re, level.eq(level - source_bits)),
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If(we & re, level.eq(level + sink_bits - source_bits)),
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),
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If(reset_reg,
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w_cnt.eq(w_cnt.reset),
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r_cnt.eq(r_cnt.reset),
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).Else(
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If(we,
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If(w_cnt == ((ring_buf_size//sink_bits) - 1),
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w_cnt.eq(w_cnt.reset),
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).Else(
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w_cnt.eq(w_cnt + 1),
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)
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),
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If(re,
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If(r_cnt == ((ring_buf_size//source_bits) - 1),
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r_cnt.eq(r_cnt.reset),
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).Else(
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r_cnt.eq(r_cnt + 1),
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)
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),
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)
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]
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# IO
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sink_cases = {}
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for i in range(ring_buf_size//sink_bits):
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sink_cases[i] = []
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for name, width in word_layout_dchar:
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src = getattr(self.sink, name)
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dst = getattr(ring_buffer, name)[width*i: width*(i+1)]
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sink_cases[i].append(dst.eq(src))
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self.sync += If(self.sink.stb, Case(w_cnt, sink_cases))
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source_cases = {}
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for i in range(ring_buf_size//source_dw):
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source_cases[i] = []
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for name, width in word_layout_dchar_4x:
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src = getattr(ring_buffer, name)[width*i: width*(i+1)]
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dst = getattr(self.source, name)
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source_cases[i].append(dst.eq(src))
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class CXPCRC32_Checker(Module):
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"""
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Verify crc in stream data packet and stream crc less output
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"""
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def __init__(self):
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self.error = Signal()
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# TODO: change to fifo style like in LiteEthMACCRCChecker to improve timinig?
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self.sink = stream.Endpoint(word_layout_dchar)
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self.submodules.buf = buf = Buffer(word_layout_dchar)
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self.source = buf.source
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# # #
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self.submodules.crc = crc = CXPCRC32(word_width)
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self.comb += crc.data.eq(self.sink.data),
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self.submodules.fsm = fsm = FSM(reset_state="INIT")
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fsm.act("INIT",
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crc.reset.eq(1),
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NextState("CHECKING"),
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)
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fsm.act("RESET",
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crc.reset.eq(1),
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self.error.eq(crc.error),
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NextState("CHECKING"),
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)
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fsm.act("CHECKING",
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If(self.sink.stb & self.sink.eop,
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# discard the crc
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self.sink.ack.eq(1),
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buf.source.eop.eq(1),
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NextState("RESET"),
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).Else(
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self.sink.connect(buf.sink),
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),
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crc.ce.eq(self.sink.stb),
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)
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#
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# 4x word pipeline
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#
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class Stream_Merger(Module):
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"""
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Merge n channels stream packet into one sequentially
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"""
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def __init__(self, layout, n_channels):
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assert n_channels > 1 # don't need a arbiter if there is only one channel
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self.active_channels = Signal(n_channels)
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self.sinks = [stream.Endpoint(layout) for _ in range(n_channels)]
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self.source = stream.Endpoint(layout)
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="0")
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# Section 9.5.5 (CXP-001-2021)
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# When Multiple connections are active, stream packets are transmitted in
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# ascending order of Connection ID
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# Support ch0->1->2->4 topology only
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for n, sink in enumerate(self.sinks):
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if n < n_channels - 1:
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fsm.act(str(n),
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sink.connect(self.source),
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If(sink.stb & sink.eop & self.source.ack,
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If(self.active_channels[n+1],
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NextState(str(n+1)),
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). Else(
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NextState(str(0)),
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),
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)
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)
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else:
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fsm.act(str(n),
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sink.connect(self.source),
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If(sink.stb & sink.eop & self.source.ack,
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NextState(str(0))
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),
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)
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