forked from M-Labs/artiq-zynq
cxp downconn: use 40bits
This commit is contained in:
parent
17277504f1
commit
49d5cad5fd
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@ -1,6 +1,5 @@
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from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.misc import WaitTimer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores.code_8b10b import Encoder, Decoder
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@ -155,43 +154,20 @@ class CXP_DownConn(Module, AutoCSR):
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self.loopback_mode = CSRStorage(3)
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self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage)
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# DEBUG: RXDATA checking
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aligned = Signal()
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valid_data = Signal()
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rx1cnt = Signal(max=11)
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comma = 0b0101111100
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comma_n = ~comma & 0b1111111111
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self.sync.cxp_gtx_rx += [
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If(self.gtx.comma_det.check_ps.o,
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aligned.eq(0),
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).Elif((gtx.comma_det.data[:10] == comma) | (gtx.comma_det.data[:10] == comma_n),
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aligned.eq(1),
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),
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rx1cnt.eq(reduce(add, [gtx.comma_det.data[i] for i in range(10)])),
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If(self.gtx.comma_det.check_ps.o,
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valid_data.eq(0)
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).Elif((rx1cnt == 4) | (rx1cnt == 5) | (rx1cnt == 6),
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valid_data.eq(1)
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),
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]
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# DEBUG: IO SMA & PMOD
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self.specials += [
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Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx),
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# pmod 0-7 pin
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Instance("OBUF", i_I=gtx.comma_det.aligner_en_rxclk, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.comma_det.rxinit_done, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=gtx.comma_det.restart, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=aligned, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=gtx.comma_det.ready, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=gtx.comma_det.check_ps.o, o_O=pmod_pads[5]),
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Instance("OBUF", i_I=valid_data, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[7]),
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Instance("OBUF", i_I=gtx.comma_det.rxinit_done, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.comma_det.restart, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=gtx.comma_det.aligner_en_rxclk, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=gtx.comma_det.check_reset, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=gtx.comma_det.comma_aligned, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=gtx.comma_det.comma_seen, o_O=pmod_pads[5]),
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Instance("OBUF", i_I=gtx.comma_det.has_error, o_O=pmod_pads[6]),
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Instance("OBUF", i_I=gtx.comma_det.ready, o_O=pmod_pads[7]),
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# Instance("OBUF", i_I=gtx.dclk, o_O=pmod_pads[0]),
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# Instance("OBUF", i_I=gtx.den, o_O=pmod_pads[1]),
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@ -200,8 +176,6 @@ class CXP_DownConn(Module, AutoCSR):
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]
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# DEBUG: datain
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counter_max = 2
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counter = Signal(max=counter_max)
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self.data_0 = CSRStorage(8)
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self.data_1 = CSRStorage(8)
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@ -222,24 +196,23 @@ class CXP_DownConn(Module, AutoCSR):
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self.decoded_k_1 = CSRStatus()
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self.sync.cxp_gtx_tx += [
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If(counter == 0,
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self.gtx.encoder.d[0].eq(self.data_0.storage),
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self.gtx.encoder.k[0].eq(self.control_bit_0.storage),
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self.gtx.encoder.d[1].eq(self.data_1.storage),
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self.gtx.encoder.k[1].eq(self.control_bit_1.storage),
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counter.eq(counter+1),
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).Elif(counter == 1,
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self.gtx.encoder.d[0].eq(self.data_2.storage),
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self.gtx.encoder.k[0].eq(self.control_bit_2.storage),
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self.gtx.encoder.d[1].eq(self.data_3.storage),
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self.gtx.encoder.k[1].eq(self.control_bit_3.storage),
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counter.eq(0),
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),
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self.gtx.encoder.d[0].eq(0xBC),
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self.gtx.encoder.k[0].eq(1),
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self.gtx.encoder.d[1].eq(0x3C),
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self.gtx.encoder.k[1].eq(1),
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self.gtx.encoder.d[2].eq(0x3C),
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self.gtx.encoder.k[2].eq(1),
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self.gtx.encoder.d[3].eq(0xB5),
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self.gtx.encoder.k[3].eq(0),
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self.encoded_0.status.eq(self.gtx.encoder.output[0]),
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self.encoded_1.status.eq(self.gtx.encoder.output[1]),
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]
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# keep it odd, so it will show data[n] where n is odd
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stb_timer = Signal(reset=10, max=11)
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self.sync.cxp_gtx_rx += [
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If(stb_timer == 0,
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self.rxdata_0.status.eq(self.gtx.decoders[0].input),
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self.decoded_data_0.status.eq(self.gtx.decoders[0].d),
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self.decoded_k_0.status.eq(self.gtx.decoders[0].k),
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@ -247,6 +220,10 @@ class CXP_DownConn(Module, AutoCSR):
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self.rxdata_1.status.eq(self.gtx.decoders[1].input),
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self.decoded_data_1.status.eq(self.gtx.decoders[1].d),
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self.decoded_k_1.status.eq(self.gtx.decoders[1].k),
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stb_timer.eq(stb_timer.reset),
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).Else(
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stb_timer.eq(stb_timer - 1),
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)
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]
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@ -295,7 +272,7 @@ class QPLL(Module):
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# refclk_div = 2
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# self.Xxout_div = 2
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self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/20
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self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/40
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self.specials += [
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Instance("GTXE2_COMMON",
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@ -352,7 +329,7 @@ class QPLL(Module):
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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class Comma_Detector(Module):
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def __init__(self, comma, check_period=150_000):
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def __init__(self, comma, check_period=1_000_000):
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self.data = Signal(20)
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self.rxinit_done = Signal()
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@ -368,87 +345,207 @@ class Comma_Detector(Module):
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# - UG476 (v1.12.1) p.228
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# The validity of data & comma are checked externally
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aligned = Signal()
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valid_data = Signal()
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aligned_rxclk = Signal()
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valid_data_rxclk = Signal()
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rx1cnt = Signal(max=11)
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self.specials += [
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MultiReg(aligned_rxclk, aligned),
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MultiReg(valid_data_rxclk, valid_data),
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]
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self.submodules.check_ps = check_ps = PulseSynchronizer("sys", "cxp_gtx_rx")
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# aligned = Signal()
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# valid_data = Signal()
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# aligned_rxclk = Signal()
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# valid_data_rxclk = Signal()
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# rx1cnt = Signal(max=11)
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# self.specials += [
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# MultiReg(aligned_rxclk, aligned),
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# MultiReg(valid_data_rxclk, valid_data),
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# ]
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# self.submodules.check_reset = check_reset = PulseSynchronizer("sys", "cxp_gtx_rx")
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comma_n = ~comma & 0b1111111111
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self.sync.cxp_gtx_rx += [
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If(check_ps.o,
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aligned_rxclk.eq(0),
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).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
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aligned_rxclk.eq(1),
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),
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# comma_n = ~comma & 0b1111111111
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# self.sync.cxp_gtx_rx += [
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# If(check_reset.o,
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# aligned_rxclk.eq(0),
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# ).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
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# aligned_rxclk.eq(1),
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# ),
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rx1cnt.eq(reduce(add, [self.data[i] for i in range(10)])),
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If(check_ps.o,
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valid_data_rxclk.eq(0),
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).Elif((rx1cnt == 4) | (rx1cnt == 5) | (rx1cnt == 6),
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valid_data_rxclk.eq(1),
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),
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]
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# rx1cnt.eq(reduce(add, [self.data[i] for i in range(10)])),
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# If(check_reset.o,
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# valid_data_rxclk.eq(0),
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# ).Elif((rx1cnt == 4) | (rx1cnt == 5) | (rx1cnt == 6),
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# valid_data_rxclk.eq(1),
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# ),
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# ]
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# self.aligned = Signal()
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# self.valid_data = Signal()
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# self.comb +=[
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# self.aligned.eq(aligned),
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# self.valid_data.eq(valid_data)
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# ]
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check_counter = Signal(reset=check_period-1, max=check_period)
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check = Signal()
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# check = Signal()
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self.sync += [
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check.eq(0),
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self.restart.eq(0),
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# check.eq(0),
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# check_reset.i.eq(0),
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If(~self.ready,
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If(check_counter == 0,
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check_counter.eq(check_counter.reset),
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check.eq(1),
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# check.eq(1),
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self.restart.eq(1),
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# check_reset.i.eq(1),
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).Else(
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check_counter.eq(check_counter - 1),
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)
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)
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]
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_COMMA_ALIGN")
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# WIP:
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aligner_en = Signal()
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self.specials += MultiReg(aligner_en, self.aligner_en_rxclk, odomain="cxp_gtx_rx")
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fsm.act("WAIT_COMMA_ALIGN",
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aligner_en.eq(1),
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If(check,
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check_ps.i.eq(1),
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If(aligned,
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NextState("WAIT_VALID_DATA"),
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comma_n = ~comma & 0b1111111111
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has_error = Signal()
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comma_aligned = Signal()
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comma_seen = Signal()
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error_seen = Signal()
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one_counts = Signal(max=11)
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counter_period = 5000
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counter = Signal(reset=counter_period-1, max=counter_period)
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check_reset = Signal()
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check = Signal()
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self.sync.cxp_gtx_rx += [
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check.eq(0),
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If(counter == 0,
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counter.eq(counter.reset),
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check.eq(1),
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).Else(
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self.restart.eq(1),
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)
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counter.eq(counter - 1),
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),
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has_error.eq(0),
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one_counts.eq(reduce(add, [self.data[i] for i in range(10, 20)])),
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If((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
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has_error.eq(1)
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),
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comma_aligned.eq(0),
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If((self.data[:10] == comma) | (self.data[:10] == comma_n),
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comma_aligned.eq(1)
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),
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# signal that need to be manually cleared
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If(check_reset,
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comma_seen.eq(0),
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).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
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comma_seen.eq(1)
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),
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one_counts.eq(reduce(add, [self.data[i] for i in range(10, 20)])),
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If(check_reset,
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error_seen.eq(0),
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).Elif((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
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error_seen.eq(1),
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),
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]
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# DEBUG: expose signal
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self.check_reset = Signal()
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self.comma_aligned = Signal()
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self.comma_seen = Signal()
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self.has_error = Signal()
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self.error_seen = Signal()
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self.comb +=[
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self.check_reset.eq(check_reset),
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self.comma_aligned.eq(comma_aligned),
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self.comma_seen.eq(comma_seen),
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self.has_error.eq(has_error),
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self.error_seen.eq(error_seen),
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]
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self.submodules.rxfsm = rxfsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="ALIGNING"))
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rxfsm.act("ALIGNING",
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self.aligner_en_rxclk.eq(1),
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If(comma_aligned & (~has_error),
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check_reset.eq(1),
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NextState("DOUBLE_CHECK"),
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)
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)
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fsm.act("WAIT_VALID_DATA",
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aligner_en.eq(1),
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rxfsm.act("DOUBLE_CHECK",
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If(check,
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check_ps.i.eq(1),
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If(aligned & valid_data,
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check_reset.eq(1),
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If(~error_seen,
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NextState("READY"),
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).Else(
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self.restart.eq(1),
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NextState("WAIT_COMMA_ALIGN"),
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NextState("ALIGNING")
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)
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)
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)
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fsm.act("READY",
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self.ready.eq(1),
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ready = Signal()
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self.specials += MultiReg(ready, self.ready)
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rxfsm.act("READY",
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ready.eq(1),
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If(check,
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check_ps.i.eq(1),
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If(~(aligned & valid_data),
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self.restart.eq(1),
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NextState("WAIT_COMMA_ALIGN"),
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check_reset.eq(1),
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If(~comma_seen,
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NextState("ALIGNING"),
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)
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)
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)
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# self.submodules.fsm = fsm = FSM(reset_state="WAIT_RXINIT")
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# aligner_en = Signal()
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# self.specials += MultiReg(aligner_en, self.aligner_en_rxclk, odomain="cxp_gtx_rx")
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# fsm.act("WAIT_RXINIT",
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# If(self.rxinit_done,
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# NextState("WAIT_COMMA_ALIGN"),
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# )
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# )
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# fsm.act("WAIT_COMMA_ALIGN",
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# aligner_en.eq(1),
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# If(check,
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# check_reset.i.eq(1),
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# If(aligned,
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# NextState("WAIT_VALID_DATA"),
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# ).Else(
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# self.restart.eq(1),
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# NextState("WAIT_RXINIT")
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# )
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# )
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# )
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# fsm.act("WAIT_VALID_DATA",
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# aligner_en.eq(1),
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# If(check,
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# check_reset.i.eq(1),
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# If(aligned & valid_data,
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# NextState("READY"),
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# ).Else(
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# self.restart.eq(1),
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# NextState("WAIT_RXINIT"),
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# )
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# )
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# )
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# fsm.act("READY",
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# self.ready.eq(1),
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# If(check,
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# check_reset.i.eq(1),
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# If(~(aligned & valid_data),
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# self.restart.eq(1),
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# NextState("WAIT_RXINIT"),
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# )
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# )
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# )
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class GTX(Module):
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# Settings:
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@ -463,7 +560,7 @@ class GTX(Module):
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# linerate = USRCLK * datawidth
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pll_fbout_mult = 8
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txusr_pll_div = pll_fbout_mult*sys_clk_freq/qpll.tx_usrclk_freq # 20 is datawidth
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txusr_pll_div = pll_fbout_mult*sys_clk_freq/qpll.tx_usrclk_freq
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self.tx_restart = Signal()
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self.rx_restart = Signal()
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@ -484,9 +581,9 @@ class GTX(Module):
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self.dout = Signal(16)
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self.dready = Signal()
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self.submodules.encoder = ClockDomainsRenamer("cxp_gtx_tx")(Encoder(2, True))
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self.submodules.encoder = ClockDomainsRenamer("cxp_gtx_tx")(Encoder(4, True))
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self.submodules.decoders = [ClockDomainsRenamer("cxp_gtx_rx")(
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(Decoder(True))) for _ in range(2)]
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(Decoder(True))) for _ in range(4)]
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# transceiver direct clock outputs
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@ -509,8 +606,8 @@ class GTX(Module):
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rx_init.cplllock.eq(qpll.lock)
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]
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txdata = Signal(20)
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rxdata = Signal(20)
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txdata = Signal(40)
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rxdata = Signal(40)
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comma_aligner_en = Signal()
|
||||
# Note: the following parameters were set after consulting AR45360
|
||||
|
|
@ -570,11 +667,11 @@ class GTX(Module):
|
|||
i_TXINHIBIT=~self.txenable,
|
||||
|
||||
# TX data
|
||||
p_TX_DATA_WIDTH=20,
|
||||
p_TX_INT_DATAWIDTH=0,
|
||||
i_TXCHARDISPMODE=Cat(txdata[9], txdata[19]),
|
||||
i_TXCHARDISPVAL=Cat(txdata[8], txdata[18]),
|
||||
i_TXDATA=Cat(txdata[:8], txdata[10:18]),
|
||||
p_TX_DATA_WIDTH=40,
|
||||
p_TX_INT_DATAWIDTH=1,
|
||||
i_TXCHARDISPMODE=Cat(txdata[9], txdata[19], txdata[29], txdata[39]),
|
||||
i_TXCHARDISPVAL=Cat(txdata[8], txdata[18], txdata[28], txdata[38]),
|
||||
i_TXDATA=Cat(txdata[:8], txdata[10:18], txdata[20:28], txdata[30:38]),
|
||||
i_TXUSRCLK=ClockSignal("cxp_gtx_tx"),
|
||||
i_TXUSRCLK2=ClockSignal("cxp_gtx_tx"),
|
||||
|
||||
|
|
@ -633,27 +730,28 @@ class GTX(Module):
|
|||
p_CLK_COR_SEQ_2_ENABLE=0b1111,
|
||||
|
||||
# RX data
|
||||
p_RX_DATA_WIDTH=20,
|
||||
p_RX_INT_DATAWIDTH=0,
|
||||
o_RXDISPERR=Cat(rxdata[9], rxdata[19]),
|
||||
o_RXCHARISK=Cat(rxdata[8], rxdata[18]),
|
||||
o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
|
||||
p_RX_DATA_WIDTH=40,
|
||||
p_RX_INT_DATAWIDTH=1,
|
||||
o_RXDISPERR=Cat(rxdata[9], rxdata[19], rxdata[29], rxdata[39]),
|
||||
o_RXCHARISK=Cat(rxdata[8], rxdata[18], rxdata[28], rxdata[38]),
|
||||
o_RXDATA=Cat(rxdata[:8], rxdata[10:18], rxdata[20:28], rxdata[30:38]),
|
||||
|
||||
# RX Byte and Word Alignment Attributes
|
||||
p_ALIGN_COMMA_DOUBLE="FALSE",
|
||||
p_ALIGN_COMMA_ENABLE=0b1111111111,
|
||||
p_ALIGN_COMMA_WORD=2, # align comma to rxdata[:10] only
|
||||
p_ALIGN_COMMA_WORD=4, # align comma to rxdata[:10] only
|
||||
p_ALIGN_MCOMMA_DET="TRUE",
|
||||
p_ALIGN_MCOMMA_VALUE=0b1010000011,
|
||||
p_ALIGN_PCOMMA_DET="TRUE",
|
||||
p_ALIGN_PCOMMA_VALUE=0b0101111100,
|
||||
p_SHOW_REALIGN_COMMA="FALSE",
|
||||
p_SHOW_REALIGN_COMMA="TRUE",
|
||||
p_RXSLIDE_AUTO_WAIT=7,
|
||||
p_RXSLIDE_MODE="OFF",
|
||||
p_RX_SIG_VALID_DLY=10,
|
||||
i_RXPCOMMAALIGNEN=comma_aligner_en,
|
||||
i_RXMCOMMAALIGNEN=comma_aligner_en,
|
||||
i_RXCOMMADETEN=1,
|
||||
i_RXSLIDE=0,
|
||||
|
||||
# RX 8B/10B Decoder Attributes
|
||||
p_RX_DISPERR_SEQ_MATCH="FALSE",
|
||||
|
|
@ -758,7 +856,7 @@ class GTX(Module):
|
|||
p_CLKFBOUT_MULT=pll_fbout_mult, p_DIVCLK_DIVIDE=1,
|
||||
i_CLKFBIN=txpll_fb_clk, o_CLKFBOUT=txpll_fb_clk,
|
||||
|
||||
# frequency = linerate/20
|
||||
# frequency = linerate/40
|
||||
p_CLKOUT0_DIVIDE=txusr_pll_div, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=txpll_clkout,
|
||||
|
||||
# Dynamic Reconfiguration Ports
|
||||
|
|
@ -784,9 +882,11 @@ class GTX(Module):
|
|||
]
|
||||
|
||||
self.comb += [
|
||||
txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])),
|
||||
txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1], self.encoder.output[2], self.encoder.output[3])),
|
||||
self.decoders[0].input.eq(rxdata[:10]),
|
||||
self.decoders[1].input.eq(rxdata[10:])
|
||||
self.decoders[1].input.eq(rxdata[10:20]),
|
||||
self.decoders[2].input.eq(rxdata[20:30]),
|
||||
self.decoders[3].input.eq(rxdata[30:]),
|
||||
]
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue