forked from M-Labs/artiq-zynq
cxp upconn: add word & char boundary transmission
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@ -7,10 +7,12 @@ from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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# CXP 2.1 section 9.2.5
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IDLE_WORDS = [
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IDLE_CHARS = [
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#[data, k]
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[0b10111100, 1], #K28.5
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[0b10111100, 1], #K28.5
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[0b10111100, 1], #K28.5
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[0b10111100, 1], #K28.5
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# [0b00111100, 1], #K28.1
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# [0b00111100, 1], #K28.1
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# [0b10111100, 0], #D28.5
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@ -66,21 +68,30 @@ class CXP_UpConn(Module, AutoCSR):
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o = Signal()
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tx_en = Signal()
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tx_bitcount = Signal(max=10)
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tx_wordcount = Signal()
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tx_reg = Signal(10)
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wordidx = Signal(max=len(IDLE_WORDS))
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disp = Signal()
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tx_wordcount = Signal(max=4)
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priority = Signal(max=nfifos)
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idling = Signal()
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# startup sequence
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self.fsm.act("WAIT_TX_ENABLE",
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If(self.tx_enable.storage,
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NextState("ENCODE_IDLE_WORD")
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NextValue(self.encoder.d, IDLE_CHARS[0][0]),
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NextValue(self.encoder.k, IDLE_CHARS[0][1]),
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NextValue(self.encoder.disp_in, 0),
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NextValue(tx_wordcount, 0),
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NextValue(tx_bitcount, 0),
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NextState("LOAD_CHAR")
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)
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)
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self.fsm.act("ENCODE_IDLE_WORD",
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NextValue(self.encoder.d, IDLE_WORDS[0][0]),
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NextValue(self.encoder.k, IDLE_WORDS[0][1]),
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NextValue(self.encoder.disp_in, 0),
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NextValue(wordidx, 1),
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self.fsm.act("LOAD_CHAR",
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NextValue(idling, 1),
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NextValue(tx_reg, self.encoder.output),
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NextValue(disp, self.encoder.disp_out),
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NextState("START_TX")
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)
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@ -91,74 +102,78 @@ class CXP_UpConn(Module, AutoCSR):
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)
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)
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# 0 lv interrupt at char boundary 10bit
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# other lv interrupt at word boundary 40bit
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cur_disp = Signal()
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# TODO: only allow trigger packet to do character interrupt and other priority level to only interrupt word
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# ISSUE: what if 2lv is transmitting 2nd char & 1lv interrupt its?
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# CXP 2.1 section 9.2.4
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self.sync.cxp_upconn += [
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self.tx_fifos.disp_in.eq(cur_disp),
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self.encoder.disp_in.eq(cur_disp),
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self.tx_fifos.disp_in.eq(disp),
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self.encoder.disp_in.eq(disp),
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self.encoder.d.eq(Array(IDLE_CHARS)[tx_wordcount][0]),
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self.encoder.k.eq(Array(IDLE_CHARS)[tx_wordcount][1]),
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If(tx_en,
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0)),
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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If(self.tx_fifos.pe.n,
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self.encoder.d.eq(Array(IDLE_WORDS)[wordidx][0]),
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self.encoder.k.eq(Array(IDLE_WORDS)[wordidx][1]),
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If(wordidx != len(IDLE_WORDS),
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wordidx.eq(wordidx + 1),
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).Else(
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wordidx.eq(0),
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),
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),
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).Elif(tx_bitcount == 9,
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# char boundary
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If(tx_bitcount == 9,
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tx_bitcount.eq(0),
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If(self.tx_fifos.pe.n,
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# idle word
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tx_reg.eq(self.encoder.output),
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cur_disp.eq(self.encoder.disp_out),
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If((~self.tx_fifos.pe.n) & (self.tx_fifos.pe.o == 0),
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# trigger packet can interrupt at char level
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tx_reg.eq(self.tx_fifos.source_data[0]),
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self.tx_fifos.source_ack[0].eq(1),
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disp.eq(self.tx_fifos.disp_out[0]),
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).Else(
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# from fifos
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tx_reg.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]),
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self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1),
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cur_disp.eq(self.tx_fifos.disp_out[self.tx_fifos.pe.o]),
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),
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)
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# at word boundary
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If(tx_wordcount == 3,
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tx_wordcount.eq(0),
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# at word boundary
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If(~self.tx_fifos.pe.n,
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idling.eq(0),
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priority.eq(self.tx_fifos.pe.o),
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self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1),
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tx_reg.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]),
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disp.eq(self.tx_fifos.disp_out[self.tx_fifos.pe.o]),
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).Else(
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idling.eq(1),
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tx_reg.eq(self.encoder.output),
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disp.eq(self.encoder.disp_out),
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)
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).Else(
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# priority zero doesn't contribute to word count
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tx_wordcount.eq(tx_wordcount + 1),
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If(~idling,
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self.tx_fifos.source_ack[priority].eq(1),
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tx_reg.eq(self.tx_fifos.source_data[priority]),
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disp.eq(self.tx_fifos.disp_out[priority]),
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).Else(
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tx_reg.eq(self.encoder.output),
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disp.eq(self.encoder.disp_out),
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)
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),
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)
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)
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).Else(
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o.eq(0)
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)
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]
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# DEBUG: remove pads
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assert len(IDLE_CHARS) == 4 #word length must be 4 chars
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self.encoded_data = CSRStatus(10)
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self.sync.cxp_upconn +=[
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If(tx_bitcount == 9,
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If(self.tx_fifos.pe.n,
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# idle word
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self.encoded_data.status.eq(self.encoder.output),
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).Else(
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# from fifos
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self.encoded_data.status.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]),
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),
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If(tx_bitcount == 0,
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self.encoded_data.status.eq(tx_reg),
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)
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]
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ninth_bit = Signal()
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eighth_bit = Signal()
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word_bound = Signal()
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idle_3 = Signal()
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idle_2 = Signal()
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p1 = Signal()
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p2 = Signal()
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self.comb += [
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eighth_bit.eq(tx_bitcount == 8),
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ninth_bit.eq(tx_bitcount == 9),
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idle_3.eq(wordidx == 3),
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idle_2.eq(wordidx == 2),
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word_bound.eq(tx_wordcount == 3),
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p1.eq(priority == 1),
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p2.eq(priority == 2),
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]
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self.specials += [
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# debug sma
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@ -170,24 +185,29 @@ class CXP_UpConn(Module, AutoCSR):
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Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]),
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Instance("OBUF", i_I=~self.tx_fifos.pe.n, o_O=pmod[2]),
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Instance("OBUF", i_I=ninth_bit, o_O=pmod[3]),
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Instance("OBUF", i_I=idle_2, o_O=pmod[4]),
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Instance("OBUF", i_I=self.tx_fifos.source_ack[0], o_O=pmod[5]),
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Instance("OBUF", i_I=idle_3, o_O=pmod[6]),
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Instance("OBUF", i_I=tx_en, o_O=pmod[7]),
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Instance("OBUF", i_I=word_bound, o_O=pmod[4]),
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Instance("OBUF", i_I=idling, o_O=pmod[5]),
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[0], o_O=pmod[6]),
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[2], o_O=pmod[6]),
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[1], o_O=pmod[7]),
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Instance("OBUF", i_I=p1, o_O=pmod[6]),
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Instance("OBUF", i_I=p2, o_O=pmod[7]),
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]
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self.symbol0 = CSR(9)
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self.symbol1 = CSR(9)
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self.symbol2 = CSR(9)
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self.sync += [
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self.tx_fifos.sink_stb[0].eq(self.symbol0.re),
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self.tx_fifos.sink_data[0].eq(self.symbol0.r),
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self.tx_fifos.sink_stb[1].eq(self.symbol1.re),
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self.tx_fifos.sink_data[1].eq(self.symbol1.r),
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self.tx_fifos.sink_stb[2].eq(self.symbol2.re),
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self.tx_fifos.sink_data[2].eq(self.symbol2.r),
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]
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class TxFIFOs(Module, AutoCSR):
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def __init__(self, nfifos, fifo_depth):
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self.disp_in = Signal()
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self.disp_out = Array(Signal() for _ in range(nfifos))
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@ -208,23 +228,23 @@ class TxFIFOs(Module, AutoCSR):
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encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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setattr(self.submodules, "tx_fifo" + str(i), fifo)
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setattr(self.submodules, "tx_encoder" + str(i), encoder)
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self.comb += [
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self.sync += [
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fifo.sink.stb.eq(self.sink_stb[i]),
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self.sink_ack[i].eq(fifo.sink.ack),
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fifo.sink.data.eq(self.sink_data[i]),
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self.source_stb[i].eq(fifo.source.stb),
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fifo.source.ack.eq(self.source_ack[i]),
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]
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self.sync.cxp_upconn += [
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encoder.d.eq(fifo.source.data[:8]),
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encoder.k.eq(fifo.source.data[8]),
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encoder.disp_in.eq(self.disp_in),
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self.disp_out[i].eq(encoder.disp_out),
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self.source_data[i].eq(encoder.output),
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]
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# reset ack after asserted
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self.sync.cxp_upconn += If(self.source_ack[i], self.source_ack[i].eq(0))
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self.source_stb[i].eq(fifo.source.stb),
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fifo.source.ack.eq(self.source_ack[i]),
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self.source_data[i].eq(encoder.output),
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# reset ack after asserted
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If(self.source_ack[i], self.source_ack[i].eq(0)),
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]
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# For FIFOs transmission priority
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self.submodules.pe = PriorityEncoder(nfifos)
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self.comb += self.pe.i.eq(self.source_stb)
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