forked from M-Labs/artiq-zynq
sim: split generator into its own file
This commit is contained in:
parent
9b967f4279
commit
473d44fd82
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@ -0,0 +1,120 @@
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from sim_pipeline import CXPCRC32
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from src.gateware.cxp_pipeline import *
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class CXPCRC32Inserter(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.crc = crc = CXPCRC32(word_dw)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act(
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"IDLE",
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crc.reset.eq(1),
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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self.sink.ack.eq(0),
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NextState("COPY"),
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),
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)
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fsm.act(
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"COPY",
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crc.ce.eq(self.sink.stb & self.source.ack),
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crc.data.eq(self.sink.data),
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(
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self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT"),
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),
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)
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fsm.act(
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"INSERT",
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self.source.stb.eq(1),
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self.source.eop.eq(1),
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self.source.data.eq(crc.value),
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If(self.source.ack, NextState("IDLE")),
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)
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class StreamPacket_Wrapper(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act(
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"IDLE",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT_HEADER_0"),
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),
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)
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fsm.act(
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"INSERT_HEADER_0",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_start"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("INSERT_HEADER_1")),
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)
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fsm.act(
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"INSERT_HEADER_1",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x01, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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fsm.act(
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"COPY",
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(
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self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT_FOOTER"),
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),
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)
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fsm.act(
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"INSERT_FOOTER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_end"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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# Simulate RX don't have eop tagged
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# self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE")),
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)
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# With KCode & 0x01*4
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class StreamData_Generator(Module):
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def __init__(self):
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# should be big enough for all test
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self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
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self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
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self.submodules.wrapper = wrapper = StreamPacket_Wrapper()
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# # #
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pipeline = [buffer, crc_inserter, wrapper]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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297
sim_pipeline.py
297
sim_pipeline.py
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@ -24,110 +24,6 @@ class EOP_Marker(Module):
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self.sink.ack.eq(~self.source.stb | self.source.ack),
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self.source.eop.eq(~self.sink.stb & last_stb),
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]
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class Stream_MetaData_Extractor(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# GOAL:
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# 0) accept four sinks??
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# 1) decode SPH, SPT
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# 2) decode Image header, line break
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# 3) verify the crc before phrasing image data downstream
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# HOW??
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# combine streams?
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# phrase linedata to sys CD
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# check stream data tag
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# only need to support mono16 for now
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self.stream_id = Signal(char_width)
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self.pak_tag = Signal(char_width)
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self.stream_pak_size = Signal(char_width * 2)
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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fsm.act(
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"WAIT_HEADER",
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NextValue(self.stream_id, self.stream_id.reset),
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NextValue(self.pak_tag, self.pak_tag.reset),
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NextValue(self.stream_pak_size, self.stream_pak_size.reset),
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_id, self.sink.dchar),
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NextState("GET_PAK_TAG"),
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),
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)
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fsm.act(
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"GET_PAK_TAG",
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If(
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self.sink.stb,
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self.sink.ack.eq(1),
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NextValue(self.pak_tag, self.sink.dchar),
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NextState("GET_PAK_SIZE_0"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_0",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[8:], self.sink.dchar),
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NextState("GET_PAK_SIZE_1"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_1",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[:8], self.sink.dchar),
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NextState("STORE_BUFFER"),
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),
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)
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fsm.act(
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"STORE_BUFFER",
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self.sink.connect(self.source),
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# both serve the same function but using the pak size I can remove eop injecter and save 1 cycle
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If(self.sink.stb,
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NextValue(self.stream_pak_size, self.stream_pak_size - 1),
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If(self.stream_pak_size == 1,
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NextState("WAIT_HEADER"),
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)
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),
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# If((self.sink.stb & self.sink.eop),
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# NextState("WAIT_HEADER"),
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# )
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)
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class Frame_Decoder(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: decode Image header, line break
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class Pixel_Decoder(Module):
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def __init__(self, pixel_format="mono16"):
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assert pixel_format == "mono16"
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: support mono16 for now?
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class Streams_Crossbar(Module):
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def __init__(self, downconns, streams_buffer):
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n_downconn = len(downconns)
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@ -205,113 +101,10 @@ class CXPCRC32(Module):
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self.error.eq(reg != self.check),
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]
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class CXPCRC32Inserter(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.crc = crc = CXPCRC32(word_dw)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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crc.reset.eq(1),
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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crc.ce.eq(self.sink.stb & self.source.ack),
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crc.data.eq(self.sink.data),
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT"),
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)
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)
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fsm.act("INSERT",
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self.source.stb.eq(1),
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self.source.eop.eq(1),
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self.source.data.eq(crc.value),
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If(self.source.ack, NextState("IDLE"))
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)
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class StreamPacket_Wrapper(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT_HEADER_0"),
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)
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)
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fsm.act("INSERT_HEADER_0",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_start"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("INSERT_HEADER_1")),
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)
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fsm.act("INSERT_HEADER_1",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x01, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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fsm.act("COPY",
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT_FOOTER"),
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),
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)
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fsm.act("INSERT_FOOTER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_end"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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# Simulate RX don't have eop tagged
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# self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE")),
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)
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# With KCode & 0x01*4
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class StreamData_Generator(Module):
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def __init__(self):
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# should be big enough for all test
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self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
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self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
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self.submodules.wrapper = wrapper = StreamPacket_Wrapper()
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# # #
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pipeline = [buffer, crc_inserter, wrapper]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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# For verifying crc in stream data packet
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class Double_Stream_Buffer(Module):
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# default size is 2 kBtyes - Section 9.5.2 (CXP-001-2021)
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def __init__(self, size=16000):
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# detect and tag end of packet for crc
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# self.submodules.eop_marker = eop_marker = EOP_Marker()
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# self.sink = eop_marker.sink
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self.sink = stream.Endpoint(word_layout_dchar)
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self.submodules.crc = crc = CXPCRC32(word_dw)
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@ -393,3 +186,93 @@ class Double_Stream_Buffer(Module):
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# last_eop = Signal()
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# self.comb += self.source.eop.eq(~last_eop & self.sink.eop)
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class Stream_Parser(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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self.stream_id = Signal(char_width)
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self.pak_tag = Signal(char_width)
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self.stream_pak_size = Signal(char_width * 2)
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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fsm.act(
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"WAIT_HEADER",
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NextValue(self.stream_id, self.stream_id.reset),
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NextValue(self.pak_tag, self.pak_tag.reset),
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NextValue(self.stream_pak_size, self.stream_pak_size.reset),
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_id, self.sink.dchar),
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NextState("GET_PAK_TAG"),
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),
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)
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fsm.act(
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"GET_PAK_TAG",
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If(
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self.sink.stb,
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self.sink.ack.eq(1),
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NextValue(self.pak_tag, self.sink.dchar),
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NextState("GET_PAK_SIZE_0"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_0",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[8:], self.sink.dchar),
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NextState("GET_PAK_SIZE_1"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_1",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[:8], self.sink.dchar),
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NextState("STORE_BUFFER"),
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),
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)
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fsm.act(
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"STORE_BUFFER",
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self.sink.connect(self.source),
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# both serve the same function but using the pak size I can remove eop injecter and save 1 cycle
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If(self.sink.stb,
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NextValue(self.stream_pak_size, self.stream_pak_size - 1),
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If(self.stream_pak_size == 1,
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NextState("WAIT_HEADER"),
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)
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),
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)
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class Frame_Decoder(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: decode Image header, line break
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class Pixel_Decoder(Module):
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def __init__(self, pixel_format="mono16"):
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assert pixel_format == "mono16"
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: support mono16 for now?
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|
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@ -1,6 +1,8 @@
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from migen import *
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from misoc.interconnect import stream
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from sim_pipeline import *
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from sim_generator import StreamData_Generator
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from src.gateware.cxp_pipeline import *
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