forked from M-Labs/artiq-zynq
downconn GW: fix tx not sending comma for long pak
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26500e620c
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@ -106,7 +106,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# DEBUG: remove cdc fifo
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# gtx rx -> fifo out -> cdc out
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fifo_out = stream.AsyncFIFO(downconn_layout, 128)
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fifo_out = stream.AsyncFIFO(downconn_layout, 512)
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self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(fifo_out)
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self.sources.append(fifo_out)
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@ -165,7 +165,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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# DEBUG: datain
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# fw -> fifo (sys) -> cdc fifo -> gtx tx
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fifo_in = stream.AsyncFIFO(downconn_layout, 128)
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fifo_in = stream.AsyncFIFO(downconn_layout, 512)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
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self.sinks.append(fifo_in)
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@ -173,16 +173,28 @@ class CXP_DownConn_PHY(Module, AutoCSR):
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txstb = Signal()
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self.specials += MultiReg(self.tx_stb.storage, txstb, odomain="cxp_gtx_tx")
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word_count = Signal(max=100)
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# JANK: fix the every 98th word got eaten
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# cnt 97 98 99 0
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# out fifo[97] IDLE IDLE fifo[99]
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# ack 1 0 0 1
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self.sync.cxp_gtx_tx += [
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fifo_in.source.ack.eq(0),
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If(word_count == 99,
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word_count.eq(word_count.reset),
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).Else(
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If(fifo_in.source.stb & txstb,
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fifo_in.source.ack.eq(1),
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If(word_count != 98, fifo_in.source.ack.eq(1)),
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word_count.eq(word_count + 1),
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)
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)
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]
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# NOTE: prevent the first word send twice due to stream stb delay
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self.comb += [
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If(fifo_in.source.stb & fifo_in.source.ack,
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If((fifo_in.source.stb & fifo_in.source.ack & (word_count != 99)),
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gtx.encoder.d[0].eq(fifo_in.source.data[:8]),
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gtx.encoder.d[1].eq(fifo_in.source.data[8:16]),
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gtx.encoder.d[2].eq(fifo_in.source.data[16:24]),
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