diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py
index 1b68853..40e9938 100644
--- a/src/gateware/cxp_downconn.py
+++ b/src/gateware/cxp_downconn.py
@@ -106,7 +106,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
             # DEBUG: remove cdc fifo
             # gtx rx -> fifo out -> cdc out
             
-            fifo_out = stream.AsyncFIFO(downconn_layout, 128)
+            fifo_out = stream.AsyncFIFO(downconn_layout, 512)
             self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(fifo_out)
             self.sources.append(fifo_out)
 
@@ -165,7 +165,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
             # DEBUG: datain
             # fw -> fifo (sys) -> cdc fifo -> gtx tx
             
-            fifo_in = stream.AsyncFIFO(downconn_layout, 128)
+            fifo_in = stream.AsyncFIFO(downconn_layout, 512)
             self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
             self.sinks.append(fifo_in)
         
@@ -173,16 +173,28 @@ class CXP_DownConn_PHY(Module, AutoCSR):
             txstb = Signal()
             self.specials += MultiReg(self.tx_stb.storage, txstb, odomain="cxp_gtx_tx")
 
+            word_count = Signal(max=100)
+
+            # JANK: fix the every 98th word got eaten
+            # cnt      97    98   99       0
+            # out fifo[97] IDLE IDLE fifo[99]
+            # ack       1     0    0       1
             self.sync.cxp_gtx_tx += [
                 fifo_in.source.ack.eq(0),
-                If(fifo_in.source.stb & txstb,
-                    fifo_in.source.ack.eq(1),
+
+                If(word_count == 99,
+                    word_count.eq(word_count.reset),
+                ).Else(
+                    If(fifo_in.source.stb & txstb,
+                        If(word_count != 98, fifo_in.source.ack.eq(1)),
+                        word_count.eq(word_count + 1),
+                    )
                 )
             ]
 
             # NOTE: prevent the first word send twice due to stream stb delay 
             self.comb += [
-                If(fifo_in.source.stb & fifo_in.source.ack,
+                If((fifo_in.source.stb & fifo_in.source.ack & (word_count != 99)),
                     gtx.encoder.d[0].eq(fifo_in.source.data[:8]),
                     gtx.encoder.d[1].eq(fifo_in.source.data[8:16]),
                     gtx.encoder.d[2].eq(fifo_in.source.data[16:24]),