cxp: add upconn packet handler proto

src/gateware/cxp.py

@@ -1,5 +1,6 @@
 from migen import *
 from misoc.interconnect.csr import *
+from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
 
 from cxp_downconn import CXP_DownConn
@@ -8,8 +9,8 @@ from cxp_upconn import CXP_UpConn
 class CXP(Module, AutoCSR):
     def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
         self.submodules.crc = CXP_CRC(8)
-        # self.submodules.upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+
-        self.submodules.upconn = LinkLayer_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        self.submodules.upconn = UpConn_Packets(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
 
         self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
         # TODO: support the option high speed upconn
@@ -17,46 +18,106 @@ class CXP(Module, AutoCSR):
         # TODO: add link layer
 
         
-class LinkLayer_UpConn(Module, AutoCSR):
+class UpConn_Packets(Module, AutoCSR):
-    def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
+    def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads, fifos_depth=64):
-        self.clk_reset = CSRStorage(reset=1)
+
+        # increment after ack
+        # for CXP 2.0 or latest, command packet need to includet tags
+        # section 9.6.1.2 (CXP-001-2021)  
+        self.tag_counts = Signal(max=0xFF)
+        self.use_tag = Signal()
+        
         self.bitrate2x_enable = CSRStorage()
         self.tx_enable = CSRStorage()
+        self.encoded_data = CSRStatus(10)
 
         # # #
 
-        self.submodules.upconn = upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, 32)
+        self.submodules.upconn = upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, fifos_depth)
 
         self.comb += [
-            upconn.clk_reset.eq(self.clk_reset.storage),
             upconn.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
             upconn.tx_enable.eq(self.tx_enable.storage),
         ]
+        self.sync += [
+            self.encoded_data.status.eq(upconn.scheduler.encoder.output),
+        ]
 
 
-        # Packets
+        # Packet FIFOs with transmission priority
-        # FIFOs with transmission priority
         # 0: Trigger packet
-        # 1: IO acknowledgment for trigger packet
-        # 2: All other packets
         self.symbol0 = CSR(9)
-        self.symbol1 = CSR(9)
-        self.symbol2 = CSR(9)
-
         self.sync += [
             upconn.tx_fifos.sink_stb[0].eq(self.symbol0.re),
             upconn.tx_fifos.sink_data[0].eq(self.symbol0.r[:8]),
             upconn.tx_fifos.sink_k[0].eq(self.symbol0.r[8]),
+        ]
 
+        
+        # 1: IO acknowledgment for trigger packet
+        self.symbol1 = CSR(9)
+        self.sync += [
             upconn.tx_fifos.sink_stb[1].eq(self.symbol1.re),
             upconn.tx_fifos.sink_data[1].eq(self.symbol1.r[:8]),
             upconn.tx_fifos.sink_k[1].eq(self.symbol1.r[8]),
+        ]
+        
+        # 2: All other packets
+        # Control is not timing dependent, all the link layer is done in firmware
 
+        # Table 54 (CXP-001-2021)
+        # Largest CXP register is 8 byte
+
+        self.symbol2 = CSR(9)
+        self.sync += [
             upconn.tx_fifos.sink_stb[2].eq(self.symbol2.re),
             upconn.tx_fifos.sink_data[2].eq(self.symbol2.r[:8]),
             upconn.tx_fifos.sink_k[2].eq(self.symbol2.r[8]),
         ]
 
+        # TODO: add a packet handler for firmware
+
+        # self.packet_type = CSRStorage(8)
+        # self.data = CSR(8)
+
+        # # CRC
+
+        # self.packet_start = CSR()
+        # self.submodules.packet_fsm = packet_fms = FSM(reset_state="IDLE")
+
+        # packet_fms.act("IDLE",
+        #     upconn.tx_fifos.sink_stb[2].eq(0),
+        #     If(self.packet_start.re,
+        #         # TODO: load it 4 times
+        #         upconn.tx_fifos.sink_stb[2].eq(1),
+        #         upconn.tx_fifos.sink_data[2].eq(0xFB), # K27.7
+        #         upconn.tx_fifos.sink_k[2].eq(1),
+        #         NextState("LOAD_PACKET_TYPE"),
+        #     )
+        # )
+
+        # packet_fms.act("LOAD_PACKET_TYPE",
+            
+        
+        # )
+
+
+        # packet_fms.act("LOAD_DATA",
+        #     upconn.tx_fifos.sink_stb[2].eq(self.data.re),
+        #     upconn.tx_fifos.sink_data[2].eq(self.data.r),
+        #     upconn.tx_fifos.sink_k[2].eq(0),
+        #     If()
+        
+        # )
+
+        
+
+
+class CXP_Packet(Module):
+    def __init__(self, max_packet_length):
+        pass
+
+
 class CXP_CRC(Module, AutoCSR):
     width = 32
     polynom = 0x04C11DB7