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upconn FW: update csr

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morgan 2025-01-14 15:03:11 +08:00
parent 0d04a3400c
commit 4250a1b432
1 changed files with 4 additions and 4 deletions
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8
src/libboard_artiq/src/cxp_upconn.rs
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@ -32,8 +32,8 @@ pub fn tx_test(channel: u8, timer: &mut GlobalTimer) {
timer.delay_us(1); timer.delay_us(1);
// DEBUG: send ctrl packet or test // DEBUG: send ctrl packet or test
(CXP[channel].tx_bootstrap_tx_write)(1); (CXP[channel].tx_writer_stb_write)(1);
(CXP[channel].tx_bootstrap_tx_testseq_write)(1); (CXP[channel].tx_writer_stb_testseq_write)(1);
// DEBUG: Trigger packet (NOTE: disconnected in Gateware) // DEBUG: Trigger packet (NOTE: disconnected in Gateware)
// (CXP[channel].upconn_trig_stb_write)(1); // send trig // (CXP[channel].upconn_trig_stb_write)(1); // send trig
@ -77,7 +77,7 @@ pub fn tx_test(channel: u8, timer: &mut GlobalTimer) {
fn preload_tx_packet(channel: u8, packet: &cxp_proto::TXPacket) { fn preload_tx_packet(channel: u8, packet: &cxp_proto::TXPacket) {
let channel = channel as usize; let channel = channel as usize;
unsafe { unsafe {
while (CXP[channel].tx_bootstrap_tx_busy_read)() == 1 {} while (CXP[channel].tx_writer_busy_read)() == 1 {}
let ptr = CXP_MEM[channel].base as *mut u32; let ptr = CXP_MEM[channel].base as *mut u32;
let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN)); let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
@ -86,6 +86,6 @@ fn preload_tx_packet(channel: u8, packet: &cxp_proto::TXPacket) {
println!("TX MEM after writing"); println!("TX MEM after writing");
cxp_proto::print_packet(&writer.get_ref()[0..40]); cxp_proto::print_packet(&writer.get_ref()[0..40]);
(CXP[channel].tx_bootstrap_tx_word_len_write)(writer.position() as u16 / 4); (CXP[channel].tx_writer_word_len_write)(writer.position() as u16 / 4);
} }
} }