forked from M-Labs/artiq-zynq
downconn GW: remove unused debug prot
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@ -13,7 +13,7 @@ from functools import reduce
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from operator import add
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class CXP_RXPHYs(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads, master=0):
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def __init__(self, refclk, pads, sys_clk_freq, master=0):
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self.qpll_reset = CSR()
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self.qpll_locked = CSRStatus()
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self.gtx_start_init = CSRStorage()
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@ -22,7 +22,7 @@ class CXP_RXPHYs(Module, AutoCSR):
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self.phys = []
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# # #
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# For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL
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# For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL - DS191 (v1.18.1) Table 9.1
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self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
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self.sync += [
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qpll.reset.eq(self.qpll_reset.re),
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