forked from M-Labs/artiq-zynq
frameline GW: remove router
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3ca9c12c50
@ -607,38 +607,3 @@ class ROI_Pipeline(Module):
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# DEBUG
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self.source = self.pipeline[-1].source
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self.comb += self.source.ack.eq(1) # simulated a proper consumer, idk why but without this it will destory timing
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class Frame_Packet_Router(Module):
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# packet size expressed in bits
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def __init__(self, downconns, framebuffer, packet_size, pmod_pads):
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n_downconn = len(downconns)
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n_buffer = len(framebuffer)
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assert n_downconn > 0 and n_buffer > 0
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self.n_ext_active = Signal(max=n_downconn)
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self.routing_table = [Signal(char_width) for _ in range(1, n_buffer)]
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# # #
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# +---------+ +-------------+
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# rx pipline ----->| | | |------> crc checker ------> raw stream data
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# | arbiter |---->| broadcaster |
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# rx pipline ----->| | | |------> crc checker ------> raw stream data
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# +---------+ +-------------+
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#
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self.submodules.arbiter = arbiter = Stream_Arbiter(n_downconn)
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self.sync += arbiter.n_ext_active.eq(self.n_ext_active)
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self.submodules.broadcaster = broadcaster = Stream_Broadcaster(n_buffer)
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for i, s in enumerate(self.routing_table):
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self.sync += broadcaster.routing_ids[i].eq(s)
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for i, d in enumerate(downconns):
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# Assume downconns pipeline already marks the eop
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self.comb += d.source.connect(arbiter.sinks[i])
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self.comb += arbiter.source.connect(broadcaster.sink)
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for i, fb in enumerate(framebuffer):
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self.comb += broadcaster.sources[i].connect(fb.sink),
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