diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index e95c391..6425469 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -308,41 +308,42 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
                 arr_csr.append(csr)
                 setattr(self, name, csr)
 
-            roi_pipeline = cdr(ROI_Pipeline())
-            self.submodules += roi_pipeline
-            framebuffers.append(roi_pipeline.pipeline[0])
+            # roi_pipeline = cdr(ROI_Pipeline())
+            # self.submodules += roi_pipeline
+            # framebuffers.append(roi_pipeline.pipeline[0])
 
             # DEBUG:
             # self.comb += roi_pipeline.pipeline[-1].source.ack.eq(1)
 
 
-            # crc_checker = cdr(CXPCRC32_Checker())
+            crc_checker = cdr(CXPCRC32_Checker())
 
-            # # TODO: handle full buffer gracefully
-            # # TODO: investigate why there is a heartbeat message in the middle of the frame with k27.7 code too???
-            # # NOTE: sometimes there are 0xFBFBFBFB K=0b1111
-            # # perhaps the buffer is full overflowing and doing strange stuff             
+            # TODO: handle full buffer gracefully
+            # TODO: investigate why there is a heartbeat message in the middle of the frame with k27.7 code too???
+            # NOTE: sometimes there are 0xFBFBFBFB K=0b1111
+            # perhaps the buffer is full overflowing and doing strange stuff             
 
-            # # it should be mem block not "cycle buffer"
-            # # self.submodules.dropper = dropper = cdr(DChar_Dropper())
-            # buffer_cdc_fifo = cdr(Buffer(word_layout_dchar)) # to improve timing
-            # cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 2**log2_int(packet_size//word_dw))
-            # self.submodules += crc_checker, buffer_cdc_fifo
-            # self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
+            # it should be mem block not "cycle buffer"
+            # self.submodules.dropper = dropper = cdr(DChar_Dropper())
+            buffer = cdr(Buffer(word_layout_dchar)) # crcchecker timinig is bad
+            buffer_cdc_fifo = cdr(Buffer(word_layout_dchar)) # to improve timing
+            cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 2**log2_int(packet_size//word_dw))
+            self.submodules += buffer, crc_checker, buffer_cdc_fifo
+            self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
 
-            # pipeline = [crc_checker, buffer_cdc_fifo, cdc_fifo]
-            # for s, d in zip(pipeline, pipeline[1:]):
-            #     self.comb += s.source.connect(d.sink)
-            # framebuffers.append(pipeline[0])
+            pipeline = [buffer, crc_checker, buffer_cdc_fifo, cdc_fifo]
+            for s, d in zip(pipeline, pipeline[1:]):
+                self.comb += s.source.connect(d.sink)
+            framebuffers.append(pipeline[0])
             
 
-            # # DEBUG:
-            # if i == 0:
-            #     self.submodules.debug_out = debug_out = RX_Debug_Buffer(word_layout_dchar, 2**log2_int(packet_size//word_dw))
-            #     self.comb += pipeline[-1].source.connect(debug_out.sink)
-            # else:
-            #     # remove any backpressure 
-            #     self.comb += pipeline[-1].source.ack.eq(1)
+            # DEBUG:
+            if i == 0:
+                self.submodules.debug_out = debug_out = RX_Debug_Buffer(word_layout_dchar, 2**log2_int(packet_size//word_dw))
+                self.comb += pipeline[-1].source.connect(debug_out.sink)
+            else:
+                # remove any backpressure 
+                self.comb += pipeline[-1].source.ack.eq(1)
 
 
         self.submodules.router = router = cdr(Frame_Packet_Router(downconns, framebuffers, packet_size, pmod_pads))