forked from M-Labs/artiq-zynq
cxp upconn & downconn firmware: packet testing
downconn FW: fix compile err
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5b4878f156
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89
src/libboard_artiq/src/cxp_downconn.rs
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89
src/libboard_artiq/src/cxp_downconn.rs
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@ -0,0 +1,89 @@
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use libboard_zynq::{println, timer::GlobalTimer};
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use log::info;
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use crate::{cxp_phys, pl::csr::CXP};
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pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys::CXP_SPEED) {
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println!("==============================================================================");
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cxp_phys::change_linerate(speed);
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unsafe {
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info!("waiting for tx&rx setup...");
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timer.delay_us(50_000);
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// info!(
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// "tx_phaligndone = {} | rx_phaligndone = {}",
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// (CXP[channel].rx_txinit_phaligndone_read)(),
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// (CXP[channel].rx_rxinit_phaligndone_read)(),
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// );
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// enable txdata tranmission thought MGTXTXP, required by PMA loopback
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// (CXP[channel].rx_txenable_write)(1);
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info!("waiting for rx to align...");
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while (CXP[channel].rx_ready_read)() != 1 {}
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info!("rx ready!");
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// cxp_proto::rx_send_test_packet(channel);
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// FIXME: why test + trig ack doesn't work well for rx??
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// cxp_proto::rx_debug_send_trig_ack(channel);
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// const DATA_MAXSIZE: usize = 253;
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// let data_size = 4; // no. of bytes
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// let data: u32 = 0xDADA as u32;
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// let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
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// data_slice[..4].clone_from_slice(&data.to_be_bytes());
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// cxp_proto::rx_debug_send(
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// channel,
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// &cxp_proto::UpConnPacket::Event {
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// conn_id: 0x1234_5678_u32,
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// packet_tag: 0x69_u8,
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// length: data_size + 3,
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// event_size: data_size,
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// namespace: 0x02_u8,
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// event_id: 0x00_6969u16,
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// timestamp: 0x1234_5678u64,
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// data: data_slice,
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// },
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// )
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// .expect("loopback gtx tx error");
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// timer.delay_us(1000); // wait packet has arrive at RX async fifo
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// if (CXP[channel].rx_trigger_ack_read)() == 1 {
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// (CXP[channel].rx_trigger_ack_write)(1);
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// info!("trig ack and cleared");
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// }
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// if (CXP[channel].rx_bootstrap_decoder_err_read)() == 1 {
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// info!("!!!!!!!DECODER ERROR!!!!!!! and cleared");
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// (CXP[channel].rx_bootstrap_decoder_err_write)(1);
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// }
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// info!("packet type = {:#06X}", (CXP[channel].rx_packet_type_read)());
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// // cxp_proto::receive(channel as u8).expect("loopback gtx rx error");
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// // cxp_proto::rx_debug_mem_print(channel);
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// // DEBUG: print loopback packets
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// const LEN: usize = 20;
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// let mut pak_arr: [u32; LEN] = [0; LEN];
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// let mut k_arr: [u8; LEN] = [0; LEN];
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// let mut i: usize = 0;
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// while (CXP[channel].rx_debug_out_dout_valid_read)() == 1 {
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// pak_arr[i] = (CXP[channel].rx_debug_out_dout_pak_read)();
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// k_arr[i] = (CXP[channel].rx_debug_out_kout_pak_read)();
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// // println!("received {:#04X}", pak_arr[i]);
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// (CXP[channel].rx_debug_out_inc_write)(1);
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// i += 1;
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// if i == LEN {
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// break;
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// }
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// }
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// info!("rx ready = {}", (CXP[channel].rx_rx_ready_read)());
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// // cxp_proto::print_packetu32(&pak_arr, &k_arr);
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}
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}
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91
src/libboard_artiq/src/cxp_upconn.rs
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91
src/libboard_artiq/src/cxp_upconn.rs
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@ -0,0 +1,91 @@
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use core::slice;
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use embedded_hal::blocking::delay::DelayUs;
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use io::Cursor;
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use libboard_zynq::{println, timer::GlobalTimer};
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use crate::{cxp_proto,
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mem::mem::CXP_MEM,
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pl::csr::{self, CXP}};
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const BUF_LEN: usize = 0x800;
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pub fn tx_test(channel: u8, timer: &mut GlobalTimer) {
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const LEN: usize = 4 * 100;
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let mut pak_arr: [u8; LEN] = [0; LEN];
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let channel = channel as usize;
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unsafe {
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// (CXP[channel].tx_trig_delay_write)(0x86);
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// (CXP[channel].tx_linktrigger_write)(0x00);
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// DEBUG: prepare the packet before tx enable to avoid overhead
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preload_tx_packet(
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channel as u8,
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&cxp_proto::TXPacket::CtrlRead {
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tag: None,
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addr: 0,
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length: 4,
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},
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);
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csr::cxp_phys::tx_enable_write(1);
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timer.delay_us(1);
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// DEBUG: send ctrl packet or test
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(CXP[channel].tx_writer_stb_write)(1);
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(CXP[channel].tx_writer_stb_testseq_write)(1);
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// DEBUG: Trigger packet (NOTE: disconnected in Gateware)
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// (CXP[channel].upconn_trig_stb_write)(1); // send trig
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// DEBUG: Trigger ACK packet
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// (CXP[channel].upconn_ack_write)(1);
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timer.delay_us(2000);
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csr::cxp_phys::tx_enable_write(0);
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// Collect data
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let mut i: usize = 0;
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// match channel {
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// 0 => {
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// while csr::cxp_phys::tx_tx0_debug_buf_dout_valid_read() == 1 {
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// pak_arr[i] = csr::cxp_phys::tx_tx0_debug_buf_dout_pak_read();
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// csr::cxp_phys::tx_tx0_debug_buf_inc_write(1);
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// i += 1;
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// if i == LEN {
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// break;
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// }
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// }
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// }
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// 1 => {
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// while csr::cxp_phys::tx_tx1_debug_buf_dout_valid_read() == 1 {
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// pak_arr[i] = csr::cxp_phys::tx_tx1_debug_buf_dout_pak_read();
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// csr::cxp_phys::tx_tx1_debug_buf_inc_write(1);
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// i += 1;
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// if i == LEN {
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// break;
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// }
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// }
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// }
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// _ => {}
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// }
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cxp_proto::print_packet(&pak_arr);
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}
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}
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fn preload_tx_packet(channel: u8, packet: &cxp_proto::TXPacket) {
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let channel = channel as usize;
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unsafe {
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while (CXP[channel].tx_writer_busy_read)() == 1 {}
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let ptr = CXP_MEM[channel].base as *mut u32;
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let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
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packet.write_to(&mut writer).expect("unstable to write to tx mem");
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// DEBUG:
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println!("TX MEM after writing");
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cxp_proto::print_packet(&writer.get_ref()[0..40]);
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(CXP[channel].tx_writer_word_len_write)(writer.position() as u16 / 4);
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}
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}
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