forked from M-Labs/artiq-zynq
si549 gateware
kasli_soc: add --with-wrpll arg to switch from si5324 to si549 kasli_soc: default to use si5435 kasli_soc: add main and helper si549 for satellite si549: add i2c and adpll programmer
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3972efc61e
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@ -26,6 +26,7 @@ import analyzer
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import acpki
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import drtio_aux_controller
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import zynq_clocking
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import si549
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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eem_iostandard_dict = {
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@ -105,7 +106,7 @@ class GTPBootstrapClock(Module):
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False, with_wrpll=False):
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self.acpki = acpki
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clk_freq = description["rtio_frequency"]
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@ -205,7 +206,7 @@ class GenericStandalone(SoCCore):
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class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False, with_wrpll=False):
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clk_freq = description["rtio_frequency"]
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has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
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@ -398,7 +399,7 @@ class GenericMaster(SoCCore):
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False, with_wrpll=False):
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clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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@ -551,14 +552,19 @@ class GenericSatellite(SoCCore):
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self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=False,
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rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
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self.csr_devices.append("siphaser")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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if with_wrpll:
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self.submodules.main_dcxo = si549.Si549(platform.request("ddmtd_main_dcxo_i2c"))
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self.submodules.helper_dcxo = si549.Si549(platform.request("ddmtd_helper_dcxo_i2c"))
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self.config["HAS_SI549"] = None
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else:
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=False,
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rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
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self.csr_devices.append("siphaser")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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gtx0 = self.gt_drtio.gtxs[0]
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platform.add_false_path_constraints(
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@ -588,6 +594,8 @@ def main():
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help="build gateware into the specified directory")
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parser.add_argument("--acpki", default=False, action="store_true",
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help="enable ACPKI")
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parser.add_argument("--with-wrpll", default=False, action="store_true",
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help="enable WRPLL")
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parser.add_argument("description", metavar="DESCRIPTION",
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help="JSON system description file")
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args = parser.parse_args()
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@ -605,7 +613,7 @@ def main():
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else:
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raise ValueError("Invalid DRTIO role")
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soc = cls(description, acpki=args.acpki)
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soc = cls(description, acpki=args.acpki, with_wrpll=args.with_wrpll)
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soc.finalize()
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if args.r is not None:
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@ -0,0 +1,278 @@
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from migen import *
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from migen.genlib.fsm import *
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from misoc.interconnect.csr import *
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class I2CClockGen(Module):
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def __init__(self, width):
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self.load = Signal(width)
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self.clk2x = Signal()
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cnt = Signal.like(self.load)
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self.comb += [
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self.clk2x.eq(cnt == 0),
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]
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self.sync += [
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If(self.clk2x,
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cnt.eq(self.load),
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).Else(
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cnt.eq(cnt - 1),
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)
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]
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class I2CMasterMachine(Module):
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def __init__(self, clock_width):
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self.scl = Signal(reset=1)
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self.sda_o = Signal(reset=1)
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self.sda_i = Signal()
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self.submodules.cg = CEInserter()(I2CClockGen(clock_width))
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self.start = Signal()
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self.stop = Signal()
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self.write = Signal()
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self.ack = Signal()
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self.data = Signal(8)
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self.ready = Signal()
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# # #
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bits = Signal(4)
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data = Signal(8)
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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self.ready.eq(1),
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If(self.start,
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NextState("START0"),
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).Elif(self.stop,
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NextState("STOP0"),
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).Elif(self.write,
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NextValue(bits, 8),
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NextValue(data, self.data),
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NextState("WRITE0")
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)
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)
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fsm.act("START0",
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NextValue(self.scl, 1),
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NextState("START1")
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)
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fsm.act("START1",
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NextValue(self.sda_o, 0),
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NextState("IDLE")
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)
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fsm.act("STOP0",
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NextValue(self.scl, 0),
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NextState("STOP1")
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)
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fsm.act("STOP1",
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NextValue(self.sda_o, 0),
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NextState("STOP2")
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)
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fsm.act("STOP2",
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NextValue(self.scl, 1),
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NextState("STOP3")
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)
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fsm.act("STOP3",
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NextValue(self.sda_o, 1),
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NextState("IDLE")
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)
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fsm.act("WRITE0",
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NextValue(self.scl, 0),
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NextState("WRITE1")
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)
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fsm.act("WRITE1",
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If(bits == 0,
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NextValue(self.sda_o, 1),
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NextState("READACK0"),
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).Else(
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NextValue(self.sda_o, data[7]),
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NextState("WRITE2"),
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)
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)
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fsm.act("WRITE2",
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NextValue(self.scl, 1),
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NextValue(data[1:], data[:-1]),
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NextValue(bits, bits - 1),
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NextState("WRITE0"),
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)
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fsm.act("READACK0",
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NextValue(self.scl, 1),
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NextState("READACK1"),
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)
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fsm.act("READACK1",
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NextValue(self.ack, ~self.sda_i),
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NextState("IDLE")
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)
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run = Signal()
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idle = Signal()
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self.comb += [
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run.eq((self.start | self.stop | self.write) & self.ready),
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idle.eq(~run & fsm.ongoing("IDLE")),
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self.cg.ce.eq(~idle),
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fsm.ce.eq(run | self.cg.clk2x),
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]
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class ADPLLProgrammer(Module):
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def __init__(self):
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self.i2c_divider = Signal(16)
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self.i2c_address = Signal(7)
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self.adpll = Signal(24)
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self.stb = Signal()
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self.busy = Signal()
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self.nack = Signal()
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self.scl = Signal()
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self.sda_i = Signal()
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self.sda_o = Signal()
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# # #
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master = I2CMasterMachine(16)
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self.submodules += master
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self.comb += [
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master.cg.load.eq(self.i2c_divider),
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self.scl.eq(master.scl),
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master.sda_i.eq(self.sda_i),
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self.sda_o.eq(master.sda_o)
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]
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fsm = FSM()
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self.submodules += fsm
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adpll = Signal.like(self.adpll)
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fsm.act("IDLE",
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If(self.stb,
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NextValue(adpll, self.adpll),
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NextState("START")
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)
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)
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fsm.act("START",
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master.start.eq(1),
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If(master.ready, NextState("DEVADDRESS"))
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)
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fsm.act("DEVADDRESS",
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master.data.eq(self.i2c_address << 1),
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master.write.eq(1),
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If(master.ready, NextState("REGADRESS"))
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)
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fsm.act("REGADRESS",
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master.data.eq(231),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA0")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA0",
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master.data.eq(adpll[0:8]),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA1")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA1",
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master.data.eq(adpll[8:16]),
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master.write.eq(1),
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If(master.ready,
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If(master.ack,
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NextState("DATA2")
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).Else(
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self.nack.eq(1),
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NextState("STOP")
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)
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)
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)
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fsm.act("DATA2",
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master.data.eq(adpll[16:24]),
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master.write.eq(1),
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If(master.ready,
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If(~master.ack, self.nack.eq(1)),
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NextState("STOP")
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)
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)
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fsm.act("STOP",
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master.stop.eq(1),
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If(master.ready,
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If(~master.ack, self.nack.eq(1)),
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NextState("IDLE")
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)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class Si549(Module, AutoCSR):
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def __init__(self, pads):
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self.i2c_divider = CSRStorage(16, reset=75)
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self.i2c_address = CSRStorage(7)
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self.adpll = CSRStorage(24)
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self.adpll_stb = CSRStorage()
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self.adpll_busy = CSRStatus()
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self.nack = CSRStatus()
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self.bitbang_enable = CSRStorage()
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self.sda_oe = CSRStorage()
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self.sda_out = CSRStorage()
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self.sda_in = CSRStatus()
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self.scl_oe = CSRStorage()
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self.scl_out = CSRStorage()
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# # #
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self.submodules.programmer = ADPLLProgrammer()
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self.comb += [
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self.programmer.i2c_divider.eq(self.i2c_divider.storage),
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self.programmer.i2c_address.eq(self.i2c_address.storage),
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self.programmer.adpll.eq(self.adpll.storage),
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self.programmer.stb.eq(self.adpll_stb.storage),
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self.adpll_busy.status.eq(self.programmer.busy),
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self.nack.status.eq(self.programmer.nack)
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]
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# I2C with bitbang/gateware mode select
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sda_t = TSTriple(1)
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scl_t = TSTriple(1)
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self.specials += [
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sda_t.get_tristate(pads.sda),
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scl_t.get_tristate(pads.scl)
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]
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self.comb += [
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If(self.bitbang_enable.storage,
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sda_t.oe.eq(self.sda_oe.storage),
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sda_t.o.eq(self.sda_out.storage),
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self.sda_in.status.eq(sda_t.i),
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scl_t.oe.eq(self.scl_oe.storage),
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scl_t.o.eq(self.scl_out.storage)
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).Else(
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sda_t.oe.eq(~self.programmer.sda_o),
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sda_t.o.eq(0),
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self.programmer.sda_i.eq(sda_t.i),
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scl_t.oe.eq(~self.programmer.scl),
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scl_t.o.eq(0),
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)
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]
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