forked from M-Labs/artiq-zynq
cxp pipeline: refactor Trigger ack to use code_src
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@ -53,59 +53,23 @@ class Trigger_ACK(Module):
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def __init__(self, layout):
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self.ack = Signal()
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self.source = stream.Endpoint(layout)
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# # #
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# Section 9.3.2 (CXP-001-2021)
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# Send 4x K28.6 and 4x 0x01 as trigger packet ack
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self.submodules.code_src = code_src = Code_Source(layout)
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self.submodules.k_code_inserter = k_code_inserter = Code_Inserter(layout)
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self.comb += [
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code_src.stb.eq(self.ack),
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code_src.data.eq(0x01),
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code_src.k.eq(0),
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k_code_inserter.data.eq(K(28, 6)),
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k_code_inserter.k.eq(1),
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cnt = Signal(max=4)
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clr_cnt = Signal()
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inc_cnt = Signal()
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self.sync += [
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If(clr_cnt,
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cnt.eq(cnt.reset),
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).Elif(inc_cnt,
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cnt.eq(cnt + 1),
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)
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code_src.source.connect(k_code_inserter.sink)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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clr_cnt.eq(1),
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If(self.ack,
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NextState("WRITE_ACK0")
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)
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)
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fsm.act("WRITE_ACK0",
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self.source.stb.eq(1),
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self.source.data.eq(K(28, 6)),
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self.source.k.eq(1),
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If(cnt == 3,
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clr_cnt.eq(1),
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If(self.source.ack, NextState("WRITE_ACK1"))
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).Else(
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inc_cnt.eq(self.source.ack)
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)
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)
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fsm.act("WRITE_ACK1",
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self.source.stb.eq(1),
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self.source.data.eq(0x01),
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self.source.k.eq(0),
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If(cnt == 3,
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self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE"))
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).Else(
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inc_cnt.eq(self.source.ack)
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)
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)
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self.source = k_code_inserter.source
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class Code_Inserter(Module):
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def __init__(self, layout, insert_infront=True, counts=4):
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@ -116,12 +80,8 @@ class Code_Inserter(Module):
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self.k = Signal.like(sink.k)
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# # #
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assert counts > 0
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# TODO: make this cleaner
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# FIX this to make it work for counts = 1
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cnt = Signal() if counts == 1 else Signal(max=counts)
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clr_cnt = Signal()
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inc_cnt = Signal()
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@ -214,7 +174,6 @@ class Packet_Wrapper(Module):
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pak_start.source.connect(pak_end.sink),
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]
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@ResetInserter()
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@CEInserter()
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class CXPCRC32(Module):
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