forked from M-Labs/artiq-zynq
frameline GW: clean up
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170e42faa6
commit
3349986656
@ -262,7 +262,6 @@ class Stream_Broadcaster(Module):
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class Frame_Header_Decoder(Module):
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def __init__(self):
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self.format_error = Signal()
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self.decode_err = Signal()
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self.new_frame = Signal()
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@ -598,7 +597,7 @@ class Pixel_Coordinate_Tracker(Module):
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If(y_r == y_max,
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pix.eof.eq(1),
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y_r.eq(0),
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y_r.eq(y_r.reset),
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).Else(
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y_r.eq(y_r + 1),
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)
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@ -629,6 +628,7 @@ class ROI(Module):
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self.out = Record([
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("update", 1),
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# registered output - can be used as CDC input
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("count", count_width),
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])
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@ -645,11 +645,12 @@ class ROI(Module):
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("count", count_width),
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]))
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for pix, roi in zip(pixel_4x, self.roi_4x):
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self.sync += [
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# TODO: replace the comparision with preprocess equal
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# e.g. pix.x == self.cfg.x0 - i
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# stage 1 - generate "good" (in-ROI) signals
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If(pix.x == self.cfg.x0,
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If(pix.x <= self.cfg.x0,
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roi.x_good.eq(1)
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),
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# NOTE: this gate doens't work as 4 pixes are coming in
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@ -693,8 +694,7 @@ class ROI(Module):
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[roi.count.eq(0) for roi in self.roi_4x],
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self.out.update.eq(1),
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self.out.count.eq(reduce(add, count_buf))
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)
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),
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]
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@ -767,7 +767,7 @@ class Pixel_Parser(Module):
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class Pixel_Pipeline(Module):
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def __init__(self, res_width, count_width):
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def __init__(self, res_width, count_width, packet_size):
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# NOTE: csr need to stay outside since this module need to be cdr in the CXP_FRAME_Pipeline module
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# NOTE: TapGeo other than 1X-1Y are not supported
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@ -777,6 +777,8 @@ class Pixel_Pipeline(Module):
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# ----/----> crc checker ------> frame header ------> Pixel Parser ------> pixel 4x
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# decoder w/ coord
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# DEBUG: adding fifo doesn't help
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# self.submodules.buffer = buffer = stream.SyncFIFO(word_layout_dchar, 2**log2_int(packet_size//word_width), True)
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self.submodules.buffer = buffer = Buffer(word_layout_dchar) # to improve timing from broadcaster
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self.submodules.crc_checker = crc_checker = CXPCRC32_Checker()
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self.submodules.header_decoder = header_decoder = Frame_Header_Decoder()
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