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frameline GW: clean up

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morgan 2025-01-17 12:39:39 +08:00
parent 170e42faa6
commit 3349986656
1 changed files with 10 additions and 8 deletions
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18
src/gateware/cxp_frame_pipeline.py
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@ -262,7 +262,6 @@ class Stream_Broadcaster(Module):
class Frame_Header_Decoder(Module): class Frame_Header_Decoder(Module):
def __init__(self): def __init__(self):
self.format_error = Signal()
self.decode_err = Signal() self.decode_err = Signal()
self.new_frame = Signal() self.new_frame = Signal()
@ -598,7 +597,7 @@ class Pixel_Coordinate_Tracker(Module):
If(y_r == y_max, If(y_r == y_max,
pix.eof.eq(1), pix.eof.eq(1),
y_r.eq(0), y_r.eq(y_r.reset),
).Else( ).Else(
y_r.eq(y_r + 1), y_r.eq(y_r + 1),
) )
@ -629,6 +628,7 @@ class ROI(Module):
self.out = Record([ self.out = Record([
("update", 1), ("update", 1),
# registered output - can be used as CDC input
("count", count_width), ("count", count_width),
]) ])
@ -643,13 +643,14 @@ class ROI(Module):
("gray", len(pixel_4x[0].gray)), ("gray", len(pixel_4x[0].gray)),
("stb", 1), ("stb", 1),
("count", count_width), ("count", count_width),
])) ]))
for pix, roi in zip(pixel_4x, self.roi_4x): for pix, roi in zip(pixel_4x, self.roi_4x):
self.sync += [ self.sync += [
# TODO: replace the comparision with preprocess equal
# e.g. pix.x == self.cfg.x0 - i
# stage 1 - generate "good" (in-ROI) signals # stage 1 - generate "good" (in-ROI) signals
If(pix.x == self.cfg.x0, If(pix.x <= self.cfg.x0,
roi.x_good.eq(1) roi.x_good.eq(1)
), ),
# NOTE: this gate doens't work as 4 pixes are coming in # NOTE: this gate doens't work as 4 pixes are coming in
@ -693,8 +694,7 @@ class ROI(Module):
[roi.count.eq(0) for roi in self.roi_4x], [roi.count.eq(0) for roi in self.roi_4x],
self.out.update.eq(1), self.out.update.eq(1),
self.out.count.eq(reduce(add, count_buf)) self.out.count.eq(reduce(add, count_buf))
),
)
] ]
@ -767,7 +767,7 @@ class Pixel_Parser(Module):
class Pixel_Pipeline(Module): class Pixel_Pipeline(Module):
def __init__(self, res_width, count_width): def __init__(self, res_width, count_width, packet_size):
# NOTE: csr need to stay outside since this module need to be cdr in the CXP_FRAME_Pipeline module # NOTE: csr need to stay outside since this module need to be cdr in the CXP_FRAME_Pipeline module
# NOTE: TapGeo other than 1X-1Y are not supported # NOTE: TapGeo other than 1X-1Y are not supported
@ -777,6 +777,8 @@ class Pixel_Pipeline(Module):
# ----/----> crc checker ------> frame header ------> Pixel Parser ------> pixel 4x # ----/----> crc checker ------> frame header ------> Pixel Parser ------> pixel 4x
# decoder w/ coord # decoder w/ coord
# DEBUG: adding fifo doesn't help
# self.submodules.buffer = buffer = stream.SyncFIFO(word_layout_dchar, 2**log2_int(packet_size//word_width), True)
self.submodules.buffer = buffer = Buffer(word_layout_dchar) # to improve timing from broadcaster self.submodules.buffer = buffer = Buffer(word_layout_dchar) # to improve timing from broadcaster
self.submodules.crc_checker = crc_checker = CXPCRC32_Checker() self.submodules.crc_checker = crc_checker = CXPCRC32_Checker()
self.submodules.header_decoder = header_decoder = Frame_Header_Decoder() self.submodules.header_decoder = header_decoder = Frame_Header_Decoder()