From 3102dd8a52c16321154d54b6c323e6c9ac0b83d7 Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 22 Aug 2024 12:49:37 +0800 Subject: [PATCH] zc706: use 4.0 period constraint to fix s/h issue --- src/gateware/zc706.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 55a90de..e33b0d7 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -698,8 +698,9 @@ class CXP_FMC(): self.csr_devices.append("cxp") # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz - platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, 3.2) - platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk, 3.2) + # 4.0 works on all CXP linerate, 3.2 has some strange setup/hold time problem even on 12.5Gbps + platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, 4.0) + platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk, 4.0) platform.add_false_path_constraints(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk) rtio_channels = []