morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

zc706: use 4.0 period constraint to fix s/h issue

This commit is contained in:
morgan 2024-08-22 12:49:37 +08:00
parent 1ddd6f4a4a
commit 3102dd8a52
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/gateware/zc706.py
View File

@ -698,8 +698,9 @@ class CXP_FMC():
self.csr_devices.append("cxp")
# max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, 3.2)
platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk, 3.2)
# 4.0 works on all CXP linerate, 3.2 has some strange setup/hold time problem even on 12.5Gbps
platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, 4.0)
platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk, 4.0)
platform.add_false_path_constraints(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk)
rtio_channels = []