cxp: add tx trigger module

src/gateware/cxp.py

@@ -8,7 +8,8 @@ from cxp_pipeline import *
 
 class CXP(Module, AutoCSR):
     def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
-        self.submodules.txcore = CXP_TX_Core(pmod_pads)
+        self.submodules.txtrig = TX_Trigger()
+        self.submodules.txcore = TX_Command_Packet(pmod_pads)
 
         self.submodules.upconn = UpConn_Packets(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
 
@@ -84,7 +85,43 @@ class UpConn_Packets(Module, AutoCSR):
 def cxp_phy_layout():
     return [("data", 8), ("k", 1)]
 
-class CXP_TX_Core(Module, AutoCSR):
+class TX_Trigger(Module, AutoCSR):
+    def __init__(self):
+        # This module is mostly control by gateware
+
+
+        # # #
+
+        self.submodules.trig_ack = trig_ack = Trigger_ACK(cxp_phy_layout())
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(cxp_phy_layout(), 64)
+
+        tx_pipeline = [ trig_ack, buf_out]
+
+        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+
+        # DEBUG: INPUT
+        self.ack = CSR()
+        self.sync += [
+            trig_ack.ack.eq(self.ack.re),
+        ]
+
+        # DEBUG: OUTPUT
+        self.inc = CSR()
+        self.dout_pak = CSRStatus(8)
+        self.kout_pak = CSRStatus()
+        self.dout_valid = CSRStatus()
+
+        self.sync += [
+            # output
+            buf_out.source.ack.eq(self.inc.re),
+            self.dout_pak.status.eq(buf_out.source.data),
+            self.kout_pak.status.eq(buf_out.source.k),
+            self.dout_valid.status.eq(buf_out.source.stb),
+        ]
+
+class TX_Command_Packet(Module, AutoCSR):
     def __init__(self, pmod_pads):
         self.packet_type = CSRStorage(8)
 
@@ -161,3 +198,5 @@ class CXP_TX_Core(Module, AutoCSR):
             Instance("OBUF", i_I=buf_out.source.stb, o_O=pmod_pads[6]),
             Instance("OBUF", i_I=buf_out.source.ack, o_O=pmod_pads[7]),
         ]
+
+