forked from M-Labs/artiq-zynq
cxp: rename upconn to upconn_phy
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47d38fce32
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30be11aef2
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@ -3,7 +3,7 @@ from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from cxp_downconn import CXP_DownConn
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from cxp_upconn import CXP_UpConn
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from cxp_upconn import CXP_UpConn_PHY
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from cxp_pipeline import *
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class CXP(Module, AutoCSR):
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@ -35,17 +35,16 @@ class UpConn_Packets(Module, AutoCSR):
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# # #
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self.submodules.upconn = upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout(), fifos_depth)
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self.submodules.upconn_phy = upconn_phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout(), fifos_depth)
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self.sync += [
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upconn.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
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upconn.tx_enable.eq(self.tx_enable.storage),
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upconn.clk_reset.eq(self.clk_reset.re),
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self.tx_busy.status.eq(upconn.tx_busy),
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upconn_phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
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upconn_phy.tx_enable.eq(self.tx_enable.storage),
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upconn_phy.clk_reset.eq(self.clk_reset.re),
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self.tx_busy.status.eq(upconn_phy.tx_busy),
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]
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self.sync += [
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self.encoded_data.status.eq(upconn.scheduler.encoder.output),
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self.encoded_data.status.eq(upconn_phy.scheduler.encoder.output),
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]
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@ -53,18 +52,18 @@ class UpConn_Packets(Module, AutoCSR):
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# 0: Trigger packet
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self.symbol0 = CSR(9)
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self.sync += [
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upconn.tx_fifos.sink[0].stb.eq(self.symbol0.re),
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upconn.tx_fifos.sink[0].data.eq(self.symbol0.r[:8]),
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upconn.tx_fifos.sink[0].k.eq(self.symbol0.r[8]),
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upconn_phy.tx_fifos.sink[0].stb.eq(self.symbol0.re),
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upconn_phy.tx_fifos.sink[0].data.eq(self.symbol0.r[:8]),
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upconn_phy.tx_fifos.sink[0].k.eq(self.symbol0.r[8]),
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]
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# 1: IO acknowledgment for trigger packet
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self.symbol1 = CSR(9)
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self.sync += [
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upconn.tx_fifos.sink[1].stb.eq(self.symbol1.re),
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upconn.tx_fifos.sink[1].data.eq(self.symbol1.r[:8]),
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upconn.tx_fifos.sink[1].k.eq(self.symbol1.r[8]),
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upconn_phy.tx_fifos.sink[1].stb.eq(self.symbol1.re),
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upconn_phy.tx_fifos.sink[1].data.eq(self.symbol1.r[:8]),
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upconn_phy.tx_fifos.sink[1].k.eq(self.symbol1.r[8]),
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]
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# 2: All other packets
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@ -75,9 +74,9 @@ class UpConn_Packets(Module, AutoCSR):
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self.symbol2 = CSR(9)
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self.sync += [
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upconn.tx_fifos.sink[2].stb.eq(self.symbol2.re),
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upconn.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]),
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upconn.tx_fifos.sink[2].k.eq(self.symbol2.r[8]),
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upconn_phy.tx_fifos.sink[2].stb.eq(self.symbol2.re),
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upconn_phy.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]),
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upconn_phy.tx_fifos.sink[2].k.eq(self.symbol2.r[8]),
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]
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# TODO: put these stuff properly instead of declaring everytime
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