From 30be11aef205c9d84828b38a293b54cde0c3f51c Mon Sep 17 00:00:00 2001 From: morgan Date: Fri, 30 Aug 2024 18:29:59 +0800 Subject: [PATCH] cxp: rename upconn to upconn_phy --- src/gateware/cxp.py | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py index 2fb8824..ac17e6f 100644 --- a/src/gateware/cxp.py +++ b/src/gateware/cxp.py @@ -3,7 +3,7 @@ from misoc.interconnect.csr import * from misoc.interconnect import stream from cxp_downconn import CXP_DownConn -from cxp_upconn import CXP_UpConn +from cxp_upconn import CXP_UpConn_PHY from cxp_pipeline import * class CXP(Module, AutoCSR): @@ -35,17 +35,16 @@ class UpConn_Packets(Module, AutoCSR): # # # - self.submodules.upconn = upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout(), fifos_depth) + self.submodules.upconn_phy = upconn_phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout(), fifos_depth) self.sync += [ - upconn.bitrate2x_enable.eq(self.bitrate2x_enable.storage), - upconn.tx_enable.eq(self.tx_enable.storage), - upconn.clk_reset.eq(self.clk_reset.re), - self.tx_busy.status.eq(upconn.tx_busy), + upconn_phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage), + upconn_phy.tx_enable.eq(self.tx_enable.storage), + upconn_phy.clk_reset.eq(self.clk_reset.re), + self.tx_busy.status.eq(upconn_phy.tx_busy), ] self.sync += [ - - self.encoded_data.status.eq(upconn.scheduler.encoder.output), + self.encoded_data.status.eq(upconn_phy.scheduler.encoder.output), ] @@ -53,18 +52,18 @@ class UpConn_Packets(Module, AutoCSR): # 0: Trigger packet self.symbol0 = CSR(9) self.sync += [ - upconn.tx_fifos.sink[0].stb.eq(self.symbol0.re), - upconn.tx_fifos.sink[0].data.eq(self.symbol0.r[:8]), - upconn.tx_fifos.sink[0].k.eq(self.symbol0.r[8]), + upconn_phy.tx_fifos.sink[0].stb.eq(self.symbol0.re), + upconn_phy.tx_fifos.sink[0].data.eq(self.symbol0.r[:8]), + upconn_phy.tx_fifos.sink[0].k.eq(self.symbol0.r[8]), ] # 1: IO acknowledgment for trigger packet self.symbol1 = CSR(9) self.sync += [ - upconn.tx_fifos.sink[1].stb.eq(self.symbol1.re), - upconn.tx_fifos.sink[1].data.eq(self.symbol1.r[:8]), - upconn.tx_fifos.sink[1].k.eq(self.symbol1.r[8]), + upconn_phy.tx_fifos.sink[1].stb.eq(self.symbol1.re), + upconn_phy.tx_fifos.sink[1].data.eq(self.symbol1.r[:8]), + upconn_phy.tx_fifos.sink[1].k.eq(self.symbol1.r[8]), ] # 2: All other packets @@ -75,9 +74,9 @@ class UpConn_Packets(Module, AutoCSR): self.symbol2 = CSR(9) self.sync += [ - upconn.tx_fifos.sink[2].stb.eq(self.symbol2.re), - upconn.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]), - upconn.tx_fifos.sink[2].k.eq(self.symbol2.r[8]), + upconn_phy.tx_fifos.sink[2].stb.eq(self.symbol2.re), + upconn_phy.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]), + upconn_phy.tx_fifos.sink[2].k.eq(self.symbol2.r[8]), ] # TODO: put these stuff properly instead of declaring everytime