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cxp upconn fw: replace crc test to pipelining

This commit is contained in:
morgan 2024-08-29 17:39:50 +08:00
parent d07a8f733d
commit 2ff59e0c30
1 changed files with 22 additions and 15 deletions
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37
src/libboard_artiq/src/cxp_upconn.rs
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@ -3,25 +3,32 @@ use libboard_zynq::{println, timer::GlobalTimer};
use crate::pl::csr; use crate::pl::csr;
pub fn crc_test() { pub fn pipeline_test(timer: &mut GlobalTimer) {
let arr = [ let arr = [
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, // CXP CRC-32 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08
0x56, 0x86, 0x5D, 0x6f, // 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, // CXP CRC-32
// 0x56, 0x86, 0x5D, 0x6f,
]; ];
let mut crc: u32; // seed = 0xFFFFFFFF
const LEN: usize = 12;
let mut pak_arr: [u8; LEN] = [0; LEN];
unsafe { unsafe {
csr::cxp::crc_en_write(1);
for a in arr.iter() { for a in arr.iter() {
csr::cxp::crc_data_write(*a); while csr::cxp::txcore_din_ready_read() == 0 {}
crc = csr::cxp::crc_value_read(); // println!("{:#04X}", *a);
println!("input = {:#04x}", *a); csr::cxp::txcore_din_pak_write(*a);
// println!("CRC NOT(val.reverse) = {:#010x}", !crc.reverse_bits());
// since the input bit are reversed when entering the crc engine, the output char need to be reversed to cancel out on the receiver side
// println!("CRC CXP = {:#010x}", crc);
println!("CRC processed = {:#010x}", csr::cxp::crc_processed_read())
} }
let mut i: usize = 0;
while csr::cxp::txcore_dout_valid_read() == 1 {
pak_arr[i] = csr::cxp::txcore_dout_pak_read();
println!("received {:#04X}", pak_arr[i]);
csr::cxp::txcore_inc_write(1);
i += 1;
}
println!("{:#04X?}", pak_arr);
} }
} }
@ -36,7 +43,7 @@ pub fn tx_test(timer: &mut GlobalTimer) {
let mut arr: [u16; LEN] = [0; LEN]; let mut arr: [u16; LEN] = [0; LEN];
unsafe { unsafe {
csr::cxp::upconn_bitrate2x_enable_write(1); // csr::cxp::upconn_bitrate2x_enable_write(1);
loop { loop {
// TODO: verify the char & word boundary thingy // TODO: verify the char & word boundary thingy
@ -45,7 +52,7 @@ pub fn tx_test(timer: &mut GlobalTimer) {
} }
csr::cxp::upconn_tx_enable_write(1); csr::cxp::upconn_tx_enable_write(1);
timer.delay_us(1); // timer.delay_us(1);
for _ in 0..3 { for _ in 0..3 {
csr::cxp::upconn_symbol0_write(D01_1); csr::cxp::upconn_symbol0_write(D01_1);